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How to set regs to generate test pattern for THS8200

Sean Lu
Prodigy 70 points
Other Parts Discussed in Thread: THS8200

Hi, 

After reading several times of the datasheet of THS8200, I am still confused with the settings on generating Test Pattern.

The resolution I want is 1024x768@60p. The question is listed below.

1. Would you please paste the regs setting?

2. Is there any requirement on the input clock?

Thx in advance!

  • 0
    TI__Genius 16810 points

    Hi,

    The internal color bar test patten can only be used for graphics formats having positive H/Vsyncs.

    The line rate, frame rate, sync widths, and sync polarites must be correct for the desired format to allow the monitor to correctly detect the input format.

    If the input clock rate does not match the standard frequency of the desired graphics format, the internal timing timing registers (line length, HSOUT width, color bar width, etc.) that are used to generte the output syncs and test pattern must be adjusted to provide the correct output timing.  Ouput timinig is determined from the input clock and these internal timing registors.

    The settings below can be use with the standard clock or pixel rate.

    ////////////////////////////////////////////////////////////////////////////////


    BEGIN_DATASET  // Appended by WinVCC4 v4.54.  Saved all registers.

    DATASET_NAME,"1024x768x75 Internal Color Bar"

    // A 78.75 MHz clock must be supplied to CLKIN

    WR_REG,THS8200,0x01,0x03,0xA3 // chip_ctl VESA Color Bars enabled, Master mode          
    WR_REG,THS8200,0x01,0x19,0xBD // csc_offset3        
    WR_REG,THS8200,0x01,0x34,0x05 // dtg_total_pixel_msb 1312 total pix/line
    WR_REG,THS8200,0x01,0x35,0x20 // dtg_total_pixel_lsb
    WR_REG,THS8200,0x01,0x36,0x00 // dtg_linecnt_msb    
    WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb    
    WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode VESA Mode          
    WR_REG,THS8200,0x01,0x39,0x33 // dtg_frame_field_msb 800 total lines/frame
    WR_REG,THS8200,0x01,0x3A,0x20 // dtg_frame_size_lsb 
    WR_REG,THS8200,0x01,0x3B,0x20 // dtg_field_size_lsb 
    WR_REG,THS8200,0x01,0x3C,0x80 // dtg_vesa_cbar_size  128pix/bar  (1024/8)
    WR_REG,THS8200,0x01,0x70,0x88 // dtg_hlength_lsb HSOUT width=136 pixels   
    WR_REG,THS8200,0x01,0x71,0x00 // dtg_hdly_msb       
    WR_REG,THS8200,0x01,0x72,0x01 // dtg_hdly_lsb       
    WR_REG,THS8200,0x01,0x73,0x07 // dtg_vlength_lsb    
    WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb       
    WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb       
    WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
    WR_REG,THS8200,0x01,0x77,0x07 // dtg_vdly2_msb      
    WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb      
    WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7A,0x01 // dtg_hs_in_dly_lsb  
    WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7C,0x01 // dtg_vs_in_dly_lsb  
    WR_REG,THS8200,0x01,0x82,0x5f // pol_cntl  +HS+VS ouputs         

    END_DATASET

    ////////////////////////////////////////////////////////////////////////////////

    ////////////////////////////////////////////////////////////////////////////////


    BEGIN_DATASET  // Appended by WinVCC4 v4.54.  Saved all registers.

    DATASET_NAME,"1280x1024x60 Internal Color Bar"

    // A 108MHz clock must be supplied to CLKIN

    WR_REG,THS8200,0x01,0x03,0xA3 // chip_ctl VESA Color Bars enabled , Master mode         
    WR_REG,THS8200,0x01,0x19,0xBD // csc_offset3        
    WR_REG,THS8200,0x01,0x34,0x06 // dtg_total_pixel_msb 1688 total pix/line
    WR_REG,THS8200,0x01,0x35,0x98 // dtg_total_pixel_lsb
    WR_REG,THS8200,0x01,0x36,0x00 // dtg_linecnt_msb    
    WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb    
    WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode VESA Mode          
    WR_REG,THS8200,0x01,0x39,0x44 // dtg_frame_field_msb 1066 total lines/frame
    WR_REG,THS8200,0x01,0x3A,0x2a // dtg_frame_size_lsb 
    WR_REG,THS8200,0x01,0x3B,0x2a // dtg_field_size_lsb 
    WR_REG,THS8200,0x01,0x3C,0xA0 // dtg_vesa_cbar_size  128pix/bar  (1280/8)
    WR_REG,THS8200,0x01,0x70,0x70 // dtg_hlength_lsb HSOUT width=112 pixels   
    WR_REG,THS8200,0x01,0x71,0x00 // dtg_hdly_msb       
    WR_REG,THS8200,0x01,0x72,0x01 // dtg_hdly_lsb       
    WR_REG,THS8200,0x01,0x73,0x04 // dtg_vlength_lsb VSOUT width    
    WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb       
    WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb       
    WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
    WR_REG,THS8200,0x01,0x77,0x07 // dtg_vdly2_msb      
    WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb      
    WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7A,0x01 // dtg_hs_in_dly_lsb  
    WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7C,0x01 // dtg_vs_in_dly_lsb  
    WR_REG,THS8200,0x01,0x82,0x5f // pol_cntl  +HS+VS ouputs         

    END_DATASET

    ////////////////////////////////////////////////////////////////////////////////

  • 0 in reply to Larry Taylor
    Prodigy 70 points

    Hi, Larry

    Thanks for reply.

    1. If I have set the THS8200 a master mode, do I still have to take care of the polarity input signals?

    2. It seems that the regs settings above are generated by a soft named "winVCC2", would you please give me a download url or just email to me?

    Thanks again.

    Sean

     

  • 0 in reply to Larry Taylor
    Prodigy 70 points

    Hi, Larry

    Thanks for reply.

    1. If I have set the THS8200 a master mode, do I still have to take care of the polarity input signals?

    2. It seems that the regs settings above are generated by a soft named "winVCC4", would you please give me a download url or just email to me?

    Thanks again.

    Sean

     

  • 0 in reply to Sean Lu
    Prodigy 70 points

    Hi, Larry

    I have found a winVCC v4.41 and get it installed.

    1. It seems that if I don't connect the THS8200 through a DB25, I can't get the detail reg settings in a cmd file. Do

    you have a version that can generate the regs settings offline?

    2. The regs setting you provided for test pattern has been proven successfully, thanks. And then I try to input a 1024x768@75 24bit RGB  to 

    THS8200, Hsync, Vsync ++, and a DE connect to FID. And configure the THS8200 in the way below, which is copied from 

    http://e2e.ti.com/support/data_converters/videoconverters/f/376/p/56103/228615.aspx#228615

    //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

     

    REG 0x03 = 0xC1 // chip_ctl            
    REG 0x19 = 0x03 // csc_offset3  CSC bypassed

    REG 0x1D = 0x00 // dtg_y_sync1         
    REG 0x1E = 0x00 // dtg_y_sync2         
    REG 0x1F = 0x00 // dtg_y_sync3         
    REG 0x20 = 0x00 // dtg_cbcr_sync1      
    REG 0x21 = 0x00 // dtg_cbcr_sync2      
    REG 0x22 = 0x00 // dtg_cbcr_sync3      
    REG 0x23 = 0x00 // dtg_y_sync_upper    
    REG 0x24 = 0x00 // dtg_cbcr_sync_upper 
            
    REG 0x1C = 0x70 // dman_cntl   30bit 4:4:4 input        
    REG 0x34 = 0x05 // dtg_total_pixel_msb 1312 pixels per line
    REG 0x35 = 0x20 // dtg_total_pixel_lsb 
    REG 0x36 = 0x80 // dtg_linecnt_msb     
    REG 0x37 = 0x01 // dtg_linecnt_lsb     
    REG 0x38 = 0x87 // dtg_mode      VESA slave      
    REG 0x39 = 0x33 // dtg_frame_field_msb 800 line per frame/field
    REG 0x3A = 0x20 // dtg_frame_size_lsb  
    REG 0x3B = 0x20 // dtg_field_size_lsb  
    REG 0x4A = 0x8C // csm_mult_gy_msb     
    REG 0x4B = 0x44 // csm_mult_bcb_rcr_msb
    REG 0x4C = 0x00 // csm_mult_gy_lsb     
    REG 0x4D = 0x00 // csm_mult_bcb_lsb    
    REG 0x4E = 0x00 // csm_mult_rcr_lsb    
    REG 0x4F = 0xC0 // csm_mode            
    REG 0x70 = 0x60 // dtg_hlength_lsb   HSOUT = 96 pixels  
    REG 0x71 = 0x00 // dtg_hdly_msb        
    REG 0x72 = 0x01 // dtg_hdly_lsb        
    REG 0x73 = 0x04 // dtg_vlength_lsb  VSOUT=3 lines ( use 1 more than desired width)   
    REG 0x74 = 0x00 // dtg_vdly_msb        
    REG 0x75 = 0x01 // dtg_vdly_lsb        
    REG 0x76 = 0x00 // dtg_vlength2_lsb    
    REG 0x77 = 0x07 // dtg_vdly2_msb       
    REG 0x78 = 0xFF // dtg_vdly2_lsb       
    REG 0x79 = 0x00 // dtg_hs_in_dly_msb   
    REG 0x7A = 0x00 // dtg_hs_in_dly_lsb , use to adjust horizontal alignment
    REG 0x7B = 0x00 // dtg_vs_in_dly_msb   
    REG 0x7C = 0x00 // dtg_vs_in_dly_lsb   
    REG 0x82 = 0xDB // pol_cntl  HSout/VSout polarities++, DE enabled in VESA mode, set to 0x5B  to disable DE operation      

     

    //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

    But it turned out that there was no signal on the Vsync_out and a 9.6kHz on Hsync_out.

    Would you please give me a hint on this?

    Thanks again!

    Sean

     

     

  • 0
    TI__Genius 16810 points

     

    Sean,

    WinVcc is for use with an EVM where I2C is transmitted via the DB25 interface.  What kind on platform are you using?  Do you have a way to communcate with the THS8200 via I2C?

    The settings pasted are in the WinVcc format, but you can determine requried registers settings from this:

                                                    Reg, Data

    WR_REG,THS8200,0x01,0x03,0xA3 // chip_ctl VESA Color Bars enabled , Master mode      

    Inpt sync poarities are "don't care" when if you are using the internally generated color bar, but output polarities ant the other timing registers must be correctly programmed.   

    What grapics format are trying to generate?

    What is the input clock frequency?

    Regards,

    Larry

     

  • 0 in reply to Larry Taylor
    Prodigy 70 points

    Hi, Larry

    Thanks for reply!

    I have successfully achieved the internal test pattern with the reg settings you provided.

    We are using a customized board which communicate with PC through a Serial Port.

    So it seems that the WinVcc is not applicable to generate the registers settings, by which I don't mean

    to use the WinVcc to directly configure the THS8200 through a DB25 port, but to generate the registers

    settings in a text file. And then I extract the registers settings from the text file and configure the THS8200 with a script.

    So is there a version of WinVcc that can generate registers settings in a text file without having the THS8200

    connected with PC?

     

    And the second problem.

    I input a VESA 1024x768@75 24bitRGB with DE enable to THS8200 and output a 1024x768@75 VGA.

    The input pixel clock is 78.75MHz.

    But somehow I can't get anything on monitor.

    And I probed the Vsync_OUT and Hsync_OUT and found there was no signal on Vsync_OUT and only a 9.6kHz on Hsync_OUT.

    The registers settings is listed below. Is there any mistake? Please give me a hint. 

    Thanks a lot!

     

    REG 0x03 = 0xC1 // chip_ctl            
    REG 0x19 = 0x03 // csc_offset3  CSC bypassed

    REG 0x1D = 0x00 // dtg_y_sync1         
    REG 0x1E = 0x00 // dtg_y_sync2         
    REG 0x1F = 0x00 // dtg_y_sync3         
    REG 0x20 = 0x00 // dtg_cbcr_sync1      
    REG 0x21 = 0x00 // dtg_cbcr_sync2      
    REG 0x22 = 0x00 // dtg_cbcr_sync3      
    REG 0x23 = 0x00 // dtg_y_sync_upper    
    REG 0x24 = 0x00 // dtg_cbcr_sync_upper 
            
    REG 0x1C = 0x70 // dman_cntl   30bit 4:4:4 input        
    REG 0x34 = 0x05 // dtg_total_pixel_msb 1312 pixels per line
    REG 0x35 = 0x20 // dtg_total_pixel_lsb 
    REG 0x36 = 0x80 // dtg_linecnt_msb     
    REG 0x37 = 0x01 // dtg_linecnt_lsb     
    REG 0x38 = 0x87 // dtg_mode      VESA slave      
    REG 0x39 = 0x33 // dtg_frame_field_msb 800 line per frame/field
    REG 0x3A = 0x20 // dtg_frame_size_lsb  
    REG 0x3B = 0x20 // dtg_field_size_lsb  
    REG 0x4A = 0x8C // csm_mult_gy_msb     
    REG 0x4B = 0x44 // csm_mult_bcb_rcr_msb
    REG 0x4C = 0x00 // csm_mult_gy_lsb     
    REG 0x4D = 0x00 // csm_mult_bcb_lsb    
    REG 0x4E = 0x00 // csm_mult_rcr_lsb    
    REG 0x4F = 0xC0 // csm_mode            
    REG 0x70 = 0x60 // dtg_hlength_lsb   HSOUT = 96 pixels  
    REG 0x71 = 0x00 // dtg_hdly_msb        
    REG 0x72 = 0x01 // dtg_hdly_lsb        
    REG 0x73 = 0x04 // dtg_vlength_lsb  VSOUT=3 lines ( use 1 more than desired width)   
    REG 0x74 = 0x00 // dtg_vdly_msb        
    REG 0x75 = 0x01 // dtg_vdly_lsb        
    REG 0x76 = 0x00 // dtg_vlength2_lsb    
    REG 0x77 = 0x07 // dtg_vdly2_msb       
    REG 0x78 = 0xFF // dtg_vdly2_lsb       
    REG 0x79 = 0x00 // dtg_hs_in_dly_msb   
    REG 0x7A = 0x00 // dtg_hs_in_dly_lsb , use to adjust horizontal alignment
    REG 0x7B = 0x00 // dtg_vs_in_dly_msb   
    REG 0x7C = 0x00 // dtg_vs_in_dly_lsb   
    REG 0x82 = 0xDB // pol_cntl  HSout/VSout polarities++, DE enabled in VESA mode, set to 0x5B  to disable DE operation      

     

  • 0 in reply to Sean Lu
    TI__Genius 16810 points

    Sean,

    We don't have another software tool for generating settings.

    Are you supplying a DE signal to the THS8200.  Your settings (REG 82h) enable DE operation.  To use without DE operation, try REG82h=5Bh and tie or force the FID pin input pin to logic low.  The THS8200 frame start up is sensitive to REG82h FID polarity setting,  FID pin logic level, and REG36h field_flip bit. 

    Are you using digital embedded input syncs or separate HSYNC and VSYNC?

    Regards,

    Larry

     

  • 0 in reply to Larry Taylor
    Prodigy 70 points

    Hi, Larry

    Thanks for reply.

    Yes, I did have a DE supplied to the THS8200. And I also used separate HSYNC and YSYNC.

    So if the THS8200 goes with DE operation, the registers settings:

    REG36H = 00H

    REG82H = DBH

    if goes without DE operation, the registers settings:

    REG36H = 00H

    REG82H = 5BH

    and the FID pin tied to logic low.

    Is my understanding right?

    And the another question.

    It is about the setting of REG03H, from the datasheet it mentions that the bit dll_bypass of REG03H is set for test purpose only, 

    but from the registers settings you provided you have set the bit.

    Is there any problem with that? And maybe I should clear it and set the REG03H = 81H?

    Thanks again!

  • 0 in reply to Sean Lu
    TI__Genius 16810 points

    Sean,

    For both cases set REG 36h = 80h and FID polarity in REG 82h (bit2) = 0.  When DE is not used, pull the FID pin to logic low.

    If embedded syncs (such as ITU bt656 interface with embedded H-bit, V-bit, and F-bit) are ever used, set REG36h=00h.  In this embedded sync case the FID input pin polarity an REG82h FID ploraity are don't care.

    We typically use REG03h = C1h for graphics modes when using VESA slave mode.

    Regards,

    Larry

     

  • 0 in reply to Larry Taylor
    Prodigy 70 points

    Hi, Larry

    Thanks for reply!

    I recently found that some registers of the THS8200 didn't maintain the default value after powered.

    For example, after powered, the REG1aH, sometime is 80H, and sometime is 00H based on the same condition.

    Is this a normal phenomenon? 

    Or is it necessary to config all writable registers after power up?

    Regards,

    Sean

  • 0 in reply to Sean Lu
    TI__Genius 16810 points

    Sean,

    This is not normal behavior.  This register should remain constant for multiple reads.  The registers that are not status readback should be set to default settings following power-up/reset and should remain constant.  Are you providing a /RESET pulse at power up?  Is it possible that you have an I2C interface problem?

    Regards,

    Larry