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DAC8760: DAC8760 communication problem

Red Yen
Expert 4360 points
Part Number: DAC8760

Hi Support team 

according to the specifications to Use 0x01 to write DAC data . Since it is 16bits resolution, I choose 0x7fff to output half level

But check that the DAC does not have a corresponding output, check that the CLR is Low

if there is a place setting error or something else

 

  • 0
    TI__Guru 53773 points

    Hi Red,

    First, you should verify if your SPI timing is correct.  The image is unclear to me, the edge timing seems wrong.  You should verify that the data is being latched on the falling edge, not the rising edge.

    Thanks,

    Paul

  • 0 in reply to Paul_Frost
    Prodigy 50 points

    Hi Paul

    I wanted to update this case.

    We only can set the frame of SPI from 4 bit to 16 bit.

    If we wanted to use more bits , we can use continuous mode.

    If I don't use continuous mode,there are a little delay between frames

    But there are some problems .

    We set 24 bit SPI command by continuous mode.

    We can't use delay in continuous mode.

    So latch don't have delay. There are the information about continuous mode.

    If I don't use continuous mode

    There are a little delay between frames.

    Do you have any advices ?

    Can you help me to resolve this problem ?

    if I set 16 bit frame command , can I work this DAC ?

  • 0 in reply to user6063790
    Prodigy 50 points

    Hi Ti

    I have 2 problems.

    1. I can set the 24 bit command by continuous mode, but the clock is more than 24.

        if the slaver use CS channel , we don't have this problems.

        because the CS is high when the clock is not required. 

    2. I can set the 24 bit command by no continuous mode ,but there is a little delay between frames.

       Maybe the delay between frames cause the DAC to fail.

    How can i resolved this problem ?

    Can the DAC  endure a little delay that does not affect the value when clock is in rising edge.

  • 0 in reply to user6063790
    TI__Guru 53773 points

    Hi,

    The delay between clock periods is not a problem.  The timing table is not being violated.  

    It is key to verify that you have 24 clock periods while the CS is low.  Extra clocks do not affect the DAC when the CS is high.

    Can you implement a readback command to confirm if you are able to communicate?  This should be the first step to ensure that the DAC is correctly implemented in your system.  Try reading back the Control register after you have enabled the output (OUTEN).

    Thanks,

    Paul