Hi team,
I
I have two questions for ADS131M04 as below.
1. When the gain of PGA >8, the recommended operating input voltage is AVDD-1.8V, while it is AVDD at PGA gain <4.
What is the negative impact when >AVDD-1.8V applied to the input at PGA gain =8?
From the absolute maximum ratings, input terminal is protected up to AVDD+0.3V, so there should be no damage, correct?
2. Regarding to the SPI 16 bit communication option(16bit data output not 24bit), does the device process 24bit internally and cutoff 8 bit at the final output stage?
I mean all the phase, gain calibration setting is done in 24bit?
regards,