ADC124S021: SCLK_Low MAX specification.

Motoyasu Hattori

Part Number: ADC124S021
Other Parts Discussed in Thread: ADS1018

Hi,

MCU SPI has to get the 16bit SPI data on Low-to-High SCLK edge on ADC124S021. But Customer wants the data as 8bit format. So MCU outputs the long low width on SCLK during between upper 8bit transfer and lower 8bit transfer, when CE is low. Can ADC device accept this sequence? Please let me know.

If you have any spec of period of SCLK_Low, please let me know.

PS. ADS1018 datasheet can find the SCLK_Low MAX specification.

Thanks and best regards,

M.HATTORI.

over 5 years ago

0 Cynthia over 5 years ago

TI__Mastermind 25020 points

Hello,

in the datasheet there doe snot seem to be a max low time limit, which leads me to believe that it should be fine to old SCLK low between the two 8 bits

Regards

Cynthia

0 Motoyasu Hattori over 5 years ago in reply to Cynthia

TI__Genius 11005 points

Cynthia-san,

ADS1018 datasheet can find the SCLK_Low MAX specification as follows: If SCLK Low is exceed 28msec, SPI reset is occurred. How about ADC124S021??

Please confirm this topic.

Thanks and best regards,
M.HATTORI.

0 Cynthia over 5 years ago in reply to Motoyasu Hattori

TI__Mastermind 25020 points

Hello,

I rechecked and looked further into it, and it seems I overlooked the duty cycle limitations.

This device uses the SCLK as the conversion clock, and has a max limit on duty cycle of SCLK at 70%.

This would set the max time that SCLK can be held low, based on the frequency of SCLK.

Regards

Cynthia

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ADC124S021: SCLK_Low MAX specification.