During the use of ads5560, it is found that the collected data value is incorrect and the duty cycle of the output CLK is also incorrect. The specific conditions are as follows:
1.Mode pin not connect , DFS pin voltage is 3 / 8 drvdd ,use 2s-complement data and parallel CMOS output
2. CLK input Refer to figure 53 of specification,input clk duty cyele 50%
3. When input 0V, the ADC value collected is 15000, and the calculated value is - 0.4V. When input 1.5V DC level, the ADC value collected is 57000, which is converted into voltage value 1.2V
4.The duty cycle of output CLK is close to 90%
5.The output CLK duty cycle does not change when the Sen pin voltage is modified
