ADC12D1620QML-SP: expected level of Fs/4 spur

Hi Franke,

In the datasheet specification table, SNR, SINAD, etc has a note on what is and is not included in the measurement.

In terms of the expected Fs/4 amplitude level, I will need to check on this.

However, it will vary based on the variability of timing mis-alignments.

Will the Fs/4 spur interfere with DC signal that you are capturing?

Regards,

Rob

Hello Rob,

Thanks for your reply. Is that -60dBFS?

We have two layouts using this part.

On the earlier one we have Fs=3200MHz, DES, DC coupled, and see Fs/4 noise equivalent to about 2 LSBs peak to peak. (-66dBFS, I believe)

On the newer one we have Fs=1600MHz, DES, DC coupled, and see Fs/4 noise equivalent to about 6 LSBs peak to peak. (-56dBFS)

(Indeed, it does bounce around somewhat.)

I'm trying to understand if the second behavior is correct.

Thanks,

Kurt

Hi Kurt,

yes, -60dBFS is correct.

On the newer one, -56dBFS is still within the window.

Can you try an experiment use the same conditions listed above but AC couple the analog input and see if this improves the Fs/4 performance?

Regards,

Rob

Hi Rob,

Thanks for the information. I don't think we can AC couple at this point. Would you expect that to improve Fs/n type spurs?

Kurt