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DAC38RF82EVM: Minimum external clock frequency ?

Nir Flysher
Expert 3367 points
Part Number: DAC38RF82EVM
Other Parts Discussed in Thread: DAC38RF82, , LMK04828

Dear Team,

My customer would like to use our DAC38RF82 with ext reference clock of 1.9GHz.

We're trying to operate this mode on the EVM without any success.
We're working in CMODE1 (Direct External Clock Mode With High Amplitude Clock).
If we take a SE clock freq of 3GHz it is working well however when we reduce the freq to 1.9GHz the DAC doesn't output anything and doesn't announce any error on neither HSDC Pro or the GUI.

While it is spec'ed on the datasheet that the differential f_DACCLK can be from 0.1 to 9GHz it is not defined anywhere on the datasheet what is the min freq for the DACCLKSE pin (the single ended DAC clock input).

Hence our questions are :

1. How can we operate the DAC38RF82EVM with ext low clock of less than 2GHz ?

Even if we fix the capacitors on the board to go through the T1 transformer - the minimum freq of this transformer is 3.5GHz.

2. Is this a limitation of the DACCLKSE minimum freq or any other device ?

Best regards,

Nir

  • 0
    TI__Guru* 91947 points

    Nir,

    The GUI is calculating the wrong divider value for the TSW14J56EVM FPGA clock. When I did a test, in the case where I was using LMF = 841, int 8x, 1 IQ pair with a 1900MHz clock, the FPGA CLKout 0 and 1 had the DCLK divider set to 4 but this really needed to be a divide by 2. After making this change, I got a valid output. HSDC Pro will show the required FPGA clock rate once you click on send. Go back to the DAC GUI and make sure the divider is set properly to create this output. Remember that the input clock provided to SMA J1 goes to a divide by 4 device before going to the LMK04828 input.

    In this example, the FPGA required a 237.5MHz clock. Taking the 1.9GHz input, divide it by 4, will result in the LMK receiving a 475MHz clock. The CLKout 0 and 1 divider then needs to be set to a "2" to create the correct frequency. 

    Regards,

    Jim