ADS1248: ADS1248 behaviour when using internal reference

Hi Rohidas,

See my comments below.

Best regards,

Bob B

Rohidas Sawant76 said:

Part Number: ADS1248

Hello,

We are using ADS1248IPWR , Sigma-Delta ADC in one of our application.

Application details as follows,

1. Input range is 0-10V and -10 to +10V.  With attenuation factor using voltage divider 0.085. i.e. when we provide 10V as input , output of voltage divider will be 0.85V. [Bob] Can you give me the resistance values you are using for the voltage divider?

2. Internal PGA gain is 2. [Bob] If you are using the internal voltage reference then the full-scale range reduces to +/- 1.024V.

3. AVDD to ADC is 2.5V, AVSS is -2.5V and DVDD is 5V.

4. Used internal reference. i.e. 2.048V. [Bob] How do you have the reference connected?  Where is VREFCOM connected and what cap value are you using from VREFOUT to VREFCOM?  This must be at least 1uF.

    When we provide 20V as input then theoretically voltage divider output will be 1.7V.  But, it is observed that at ADC input is around 1.38V and it is observed that ADC raw counts starts decreasing (Roll over) once ADC input voltage reached to 1.38Voltage. [Bob]  Just so I'm clear, you are applying 20V to the voltage divider and are expecting 1.7V at the input to the ADS1248.  Is 1.38V being measured at the input of the ADS1248 with an external voltmeter?  In any case, the input exceeds the input range of the ADS1248 at a gain of 2.  The maximum input voltage is 1.024V, and you should observe 0x7FFFFF once you have reached this input voltage.

Query 1:- What will be behaviour of ADS1248 when input voltage (Vin * PGA) rises above Internal reference 2.048V. [Bob] This will depend on the amount of gain applied.  The full-scale range(FSR) is determined by +/- (VREF/GAIN) which is much easier to consider instead of Vin*PGA as it relates to the reference.  In your use case the FSR is +/-1.024V which is your measurement range.  If you exceed this range you will see 0x7FFFFF when +1.024V is exceeded and 0x800000 when -1.024V is reached.  It may be possible that once you have greatly exceeded the input range that some odd behavior may take place due to the repetitive nature of the modulator.  Also consider the input range as it relates to the output of the PGA, which relates more to the formula you have given as Vin*PGA.  Your common-mode is AGND and you are attempting to drive the PGA beyond the supply (Vin = 1.7V * Gain = 2 or 3.4V for AVDD = 2.5V).  So the outcome is invalid. 

Query 2:- What will be behaviour of ADS1248 when input voltage (Vin * PGA) rises above AVDD (2.5V) [Bob]  This is an invalid condition.  As I just explained you are attempting to drive the PGA beyond the supply rail and the outcome result is invalid and the result unpredictable as the PGA is outside of linear operation.  Usually you will see a full-scale result, but at some point the overload may be significant to cause the modulator to be unstable.

Query 3:- How to lock ADC counts when Input voltage rises above Reference voltage without count roll over. [Bob] As I stated previously, a voltage that exceeds the FSR will show FS (and should clip larger input voltages that exceed FS).  If the input is grossly exceeding the valid measurement range (either +FS or -FS), then the result is unpredictable.  If the input range due to common-mode is violated the result is also unpredictable.  Avoid conditions where the input range violates FS/Gain or common-mode input restrictions are violated for the PGA.

Please do needful on high priority.

Thankyou for understanding.