• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 45 subscribers
  • Views 535 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8684A: ADS8684A

yuquan li1
Prodigy 50 points
Part Number: ADS8684A

SPI mode  to  write and read ADS 8864A:

ADS8684A / MCU interace to it /SPI mode

page 37 says the AD converter will latch on falling edge also will drive SDO on falling edge
two different SPI mode for MCU to wrtie and read ?

clock idle is low,

AD converter will latch on falling edge, thus MCU needs SPI mode 1

but AD convertr will drive on falling edge, need MCU to latch on rising edge, MCU need SPI 0

Thanks

  • 0
    TI__Mastermind 45715 points

    Hi yuquan,

    The ADS86xx ADC device requires SPI serial communication in mode 1 (CPOL = 0, CPHA = 1), the MCU or CPU should retrieve the data during tHT_CKDO period.

    Thanks

    Regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 50 points

    Hello Dale:

    From page 11 -figure one data sheet, 

    I can tell the hold time  ( SCLK falling to (previous) data valid on SDO) - is 10 ns ( min) 

    That means micro-controller ( SPI mode -1) only has 10 ns time to latch the data on SDO line.

    I am not sure MCU can do that ?

    I tried to use MCU- SPI mode 1 to drive SDI and then switch to MCU-SPI Mode 0 to latch SDO . and it is working.

    More comment ?

    Thanks

    Yuquan

  • 0 in reply to yuquan li1
    TI__Mastermind 45715 points

    Hi Yuquan,

    Many microcontrollers can capture the data regarding tHT_CKDO period including TI's TMS320 series MCU. However, it's good to check before you select microcontroller and design your circuit. 

    When you switch your SPI mode from Mode 1 to Mode 0, this means that your are capturing the data on SDO at the rising edge of SCLK, the minimum  tSU_DOCK(setup time: SDO data valid to SCLK falling) is 25ns, hence you are capturing the data during setup time instead of hold time (the data may be correct) or you may be capturing the higher bit.

    Regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 50 points

    Hi Dale:

    At the clock falling edge , the AD converter will drive/change the SDO line.

    10ns ( hold time) after the falling edge, the line data will be  in a process to change its value.

    Since, AD converter is driving the SDO at falling  edge, thus, at  the next  rising edge, the data should be stable for MCU to capture. 

    I would think we will have more time margin to capture the data if we do it at the rising edge. I am trying to use low SPI speed ( 1.25MHz) .

    Comment ?

    Thanks a lot .

    Thanks

  • 0 in reply to yuquan li1
    TI__Mastermind 45715 points

    Hi yuquan,

    The hold time (tHT_CKDO) is only 10ns, next bit(not current bit) will be shown up at the following rising edge of SCLK, see the timing in figure 1 in datasheet.

    Thanks&Regards,

    Dale 

  • 0 in reply to Dale Li
    Prodigy 50 points

    Hello Dale:

    Page 39, Figure  91, it says At the 16th falling edge, 

    the MSB of the conversion data is output on the SDO line and can be read by the host processor on the
    subsequent falling edge of the SCLK signal.
     
    Since MSB is clocked out at the 16th falling edge, thus, I can read it out  on the next rising edge.
    Comment?
    Thanks
  • 0 in reply to yuquan li1
    TI__Mastermind 45715 points

    Hi,

    Reading the data on SDO at the falling edge of SCLK during tHT_CKDO hold time is recommended for ADS8684A ADC,  mode 1(CPOL= 0, CPHA =1) for SPI serial communication is recommended for this ADC.

    Regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 50 points

    Thanks. The MCU we have require minimal hold time 6.5ns in order to latch the data .  The ADC can have hold time >10ns.

    so , might be ok.