Hello
I want to verify my setup, see the figure below:
DACCLK = 960MHz
DAC data rate is 240MSPS, meaning that each dac is updating at 60MSPS
DATACLK is 120MHz DDR
Interpolation is x4 (240MSPS x 4 = 960MHz)
is this setup correct?
Thanks
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Hello
I want to verify my setup, see the figure below:
DACCLK = 960MHz
DAC data rate is 240MSPS, meaning that each dac is updating at 60MSPS
DATACLK is 120MHz DDR
Interpolation is x4 (240MSPS x 4 = 960MHz)
is this setup correct?
Thanks
So going back to the original plot, is the correct description is:
DACCLK = 960MHz
DAC data rate is 60MSPS, meaning that each dac is updating at 60MSPS
DATACLK is 120MHz DDR
Interpolation is x16 (60MSPS x 16 = 960MHz)
Thanks
Hi Izik,
Yes, according to the original description, the interpolation is 16x.
My drawing is based on your other description of 4x interpolation (with my assumption that you want to achieve 240MSPS of data transfer rate).
-Kang