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ADC12DJ3200: Length Matching between data lanes of 3 ADC12DJ3200 for Synchronization

LALIT VERMA
Expert 1695 points
Part Number: ADC12DJ3200

Hi,

We are using three ADC12DJ3200 in our design. We need synchronization between three ADCs and also deterministic latency.

So I want to know  the length matching requirements (in mils or ps) between: 

1. Data lanes of all three ADCs going to single FPGA through FMC connector.

2. DEVLCK and SYSREF going to three ADCs and FPGA.

Also does SYNC coming from FPGA to ADCs needs to be length matched with any clock (DEVCLK or SYSREF)?

An early response will be highly appreciated.

Thanks,

Lalit

  • 0
    TI__Mastermind 38240 points

    Hi Lalit,

    When synchronizing multiple converters. It is best to length match all of the clocks as close as possible to half the period of the sample rate. So for 3.2GSPS, that would be ~150pSec. Depending on the board material/dielectric you are working with will determine the length.

    As for the digital outputs, you have more room for "slop" typically the FPGA will have an auto-alignment employed in the JESD interface. I would try to be within 200-300mils max between all the outputs used.

    Hope this helps.

    Regards,

    Rob