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ADS5294: Some chips will not lock PLL state at 10MHz

Part Number: ADS5294

We are using the ADS5294 chips within one of our PCB designs and we have recently discovered that some of the chips (~5% of the PCBs manufactured PCBs exhibit this issue) will not lock PLL state when clocked at 10MHz. The result is corrupted output data since the chip keeps toggling states and never settles, even over a ~10 second period.

In the faulty 5% of our PCB batch (there are 3 ADS5294 devices per PCB) 2 of the chips operate correctly, 1 does not. The faulty chip can be made stable if it is heated up to a temperature of ~ 60 degrees C however as soon as it cools down the PLL state toggling re-commences. Increasing the clock frequency of the chip will also stop the state toggling however the device remains temperature sensitive and if cooled down (using freezer spray) it will start state toggling again. All faulty chips behave in this way, the only difference between chips is at what temperature the state toggling occurs.

Fully functional chips do not exhibit any of this behaviour. We are investigating with the manufacturer if there are installation issues that are damaging the chips.

To fix the issue we have placed the PLL into a fixed state and this results in the chips no longer toggling state and providing uncorrupted data, however we are concerned that we are simply covering up an issue with the chip that may results in total chip failure sooner than expected.

Couple of questions:

1) Is this an issue that you have seen before?
2) Can you provide details on the soldering limits handling for this chip?
3) We assume this is associated with the frequency detection part of the PLL, can you provide any further information about how this works?

4) Can you provide a reason for the failure mode seen in these chips and confirm that by simply disabling the auto sensing of clock frequency the chip will still maintain its performance as defined in the data sheet?
 
Any help you can provide on this issue would be gratefully received.

Regards

Mark

  • Hi Mark,

    Thanks for using ADS5294 devices.

    For your concern, I have forwarded your questions to our group engineers.

    They will reply to you soon.

    Thank you!

    Best regards,

    Chen

  • Hi Mark,

    From your application, please look at the data sheet mentioned:

    our engineer suggests:

    ===================

    ===================

    Thank you!

    Best regards,

    Chen

  • Chen,

    Thanks for the reply. We have indeed moved to fixed state 1 and this makes all chips work.

    My question however is slightly different to how we fix the issue, it is why are some chips not the same as other chips?

    ~5% of the installed chips will not settle when placed into auto mode, the other 95% will settle quickly, without issue and are not sensitive to .

    Given this information I believe there are 2 possible issues here, the first is that the chips are faulty when delivered (unlikely).

    The 2nd option is that we are over stressing the chips when they are surface mounted, possibly by using an incorrect re-flow profile.

    However to only break the frequency detection part of the chip (and only affect 1 chip out of 3) and nothing else seems unlikely, unless there is a very sensitive component within the frequency detection part and this breaks long before any other part of the chip?

    So I have 3 requests:

    1) Can you let us know the temperature reflow profile that should be used for these chips so that we can check our manufacturing stage?

    2) Are you able to provide any further details of the CLOCKGEN part of the chip? Does this contain an OCXO for example?

    3) When placing the chip into fixed state 1 does this bypass part of the chip?

    As an aside we are using decimation by 4 on all the chips so we are no where near a threshold (10MHz vs. 48MHz threshold).

    Regards

    Mark

  • Hi Mark,

    Yes, I will forward your questions to our group.

    Before that, could you please answer the following

    so our engineer replies more accurately for you?

    Thank you!

    1) According to your replies,

    you are using decimation filter by 4, right?

    (Please double confirm your register settings from Page 33 and Page 55.)

    2) If correct, please also look at and confirm from page 57, page 58 and page 44.

    you are setting the Address=0x38,

    DATA_RATE<1>="1" and DATA_RATE<0>="0" 

    right?

    3) Please refer to Page 38 and Page 39,

    every time after Powering-up all ADS5294 devices,

    Register Initialization Must be done at first before setting other registers.

    Please confirm this.

    4) Since you are using decimation filter by 4 (shown on page 33 and page 55),

    So what your CLKP and CLKN clock frequency is?

    Are CLKP and CLKN = 40MHz?

    and the internal clock rate (due to decimation rate set by 4) should become 10MHz?

    right?

    Thank you very much!

    Best regards,

    Chen

  • Chen,

    Many thanks for the reply and looking into his for us. In answer to your questions:

    1. We are using decimation by 4.

      1. Register settings are “0x2E 01 11” (same for all other channels) and “0x38 00 02”

      2. Custom filters (5A to B9) are not used.

    2. 0x38 is indeed set to DATA_RATE<1>="1" and DATA_RATE<0>="0 (0x38 00 02)

    3. After device power up the first message sent is 0x00 00 00.

      1. We do not reset the device after boot up (future builds will now include this)

      2. I have just tested including the reset message before programming the card and it does not remedy this issue.

    4. Our CLKP/CLKN frequency is 10 MHz, giving an output data rate of 2.5MHz.

    Regards

    Mark

  • Hi Mark,

    For your question, here are the reply from our engineer.

    Thank you, please take a look:

    ==========

    The PLL supports different range of frequency lock range and it changes its range based on the ADC clock frequency. When auto range mode of PLL is used, the PLL tries to switch the range automatically. In case of input clock frequency is near to the switching threshold then PLL becomes unstable. Also the range detection logic can have some offset across devices. So when customer uses 10MHz clock then for some device (5%) the threshold of PLL range switching is coming very near to 10MHz clock frequency because of which PLL becomes unstable. After writing the fixed auto range bits if device recovers then device is not getting damaged.

    ==========

    Thank you!

    Best regards,

    Chen

  • Chen,

    Many thanks for the reply. To summarise, natural variations in chip manufacture are causing the issue and putting the chips into fixed mode eliminates this issue. These chips that have this offset are not damaged and can be used without any other issues.

    Once again many thanks for taking the time to look into this issue and set my mind at rest.

    Regards

    Mark