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ADS4245: Using clock with low duty cycle

Nir Flysher
Expert 3367 points
Part Number: ADS4245

Hi Team,

My customer would like to use the ADS4245, could you please advise regarding below question :

"I’d like to feed the device input clock by external clock of 36MHz  with duty cycle of 33%.

I’ve noticed in the datasheet (see figure below) that the minimum duty cycle is 35% (or 40%). It means I’m out of spec…

How does it influence ADC performances ?"

Best regards,

Nir.

  • 0
    TI__Guru* 91947 points

    Nir,

    There is a duty cycle corrector circuit (DCC) at the input clock path which maintains a 50% duty cycle for the ADC. It works on one edge and predicts the other by using internal delay cells.

    At low clock speeds, clock period increases and the delay becomes insufficient to predict the other edge, therefore it is suggested to bypass the DCC at lower speeds.

     

    Figure 79 of the datasheet shows the impact on performance for ADS4245 at 65MSPS.

     

    Since the customer wants to operate at 36Msps, the performance will degrade more rapidly with duty cycle’s deviation from 50%. Other than impact on performance, the output timing may also get impacted.

     

    Regards,

     

    Jim

     

  • 0 in reply to jim s
    TI__Expert 3367 points

    Thanks for the explanation Jim.

    Regards,

    Nir.

  • 0
    TI__Guru* 78404 points

    Hi Nir,

    I recall for the ADS62Pxx and ADS42xx family when operating in low frequency mode, the design has to disable the internal DLL (delay lock loops) to ensure proper internal logic setup/hold time. If the external clock duty cycle is off, the internal logic may use falling edges to catch data, and may cause bad setup/hold time. This may show up as SNR hit. Let me check with Jim to see if he has done such measurements before.

    -Kang

  • 0 in reply to Kang Hsia
    TI__Guru* 91947 points

    Nir,

    I have not done any measurements while adjusting the clock duty cycle.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Expert 3367 points

    Jim, Kang,

    I understand.

    Thanks for your support.

    We will try to find another was of dividing the clock down.

    I will let you know if we need any additional support on this.

    Regards,

    Nir.