ADC10DV200: setup/hold timing issue

Gilad Aloni

Part Number: ADC10DV200

I am using ADC10DV200 in LVDS output mode.

I have difficulty to comply timing demands and I am looking for relief in the setup/hold timing demands.

I saw that the setup/hold timing demands is 0.7ns from DRDY, but in condition of 200MHz clock. Since my clock is 160MHz then I would like to know, weather, I can assume longer setup and/or hold?

Thanks Gilad

over 4 years ago

0 dBrock over 4 years ago

TI__Genius 12780 points

Hi Gilad,

Yes, setup and hold time for DRDY and Data lines will scale with the sampling frequency. If you lower the sampling rate, the setup/hold requirements for the data will increase proportionately.

Best Regards,

Dan

0 Gilad Aloni over 4 years ago in reply to dBrock

Prodigy 50 points

how do you calc it (1 or 2)?

1. half cycle is 3.125ns (for 160MHz) and 2.5ns (for 200MHz) - the difference between cycle time is 0.625ns. half from this to setup and half to hold. this means 0.7+0.625/2=1.0125ns

2. 200/160=1.25. this means setup and hold of 0.7*1.25=0.875ns

Thanks Gilad

0 dBrock over 4 years ago in reply to Gilad Aloni

TI__Genius 12780 points

Hi Gilad,

Yes, your calculations look correct.

Best Regards,

Dan

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ADC10DV200: setup/hold timing issue