• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 301 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC5662: Settling time

Steve Widener
Genius 11010 points
Part Number: DAC5662

The settling time specification for the DAC 5662 test condition refers to a mid-scale transition and is specified at 20nsec typical.

Please elaborate, does this mid scale transition infer that the DAC output goes form 0 out to midscale for the measurement or is it something else?

  • 0
    TI__Mastermind 18095 points

    Steve:

    Mid-scale transition settling time refers to the condition where the DAC transitions from x1FFF to x2000 corresponding to b0111...1 to b1000...0.  This represents the worse case scenario where every bit is transitioning at once.

    --RJH