Hello,
I am using ADS52j90 to sample data from a custom ASIC.
I use it 32 input channel mode, with 4 CML output lanes and 12-bit resolution.
So from my calculation, I should have a 6 (F) Octet configuration. Which would mean per single sample shot each lane would output (12x4) 48 bits of data.
That would be 192 bits in total for 16 input and in the next clock cycle another 192 bits, totalling to 384 bits for 32 inputs.
So my question is how is this data mapped/ordered into the AXI interface? Are zeroes padded?
I seem to not understand this.
Thanks in advance.
Cheers
