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Original question:

ADS131A04: power up only return 0xffff in daisy chain

ADS131A04: Multiple Devices Synchronous Slave Mode

Shada Safa
Prodigy 110 points
Part Number: ADS131A04

Hello, 

I am using two ADS131A04 devices chained as in Figure. 100 Pg. 73 of the datasheet.

The schematic is similar to the one done in the evaluation board of ADS131A04EVM.

I am using Synchronous Slave Mode, 24 bits, Hamming Code off.

We are using the default dynamic frame, and CRC is disabled.

I am using a free running SCLK (CLK1 0Dh), and using an FPGA to communicate/control through SPI interface.

I am able to configure all the registers and see expected response from both devices up until I send the ADC enable command/

My problem is when I send ADC enable 24h'4F0F00, I only get back a response from the first device. This is what I get back 24h'2F0F00 and 16 bytes zeros then (2224)h.

I see that I am unable to have the second device enabled as only the first one sends back a response.

  • 0
    TI__Guru* 97865 points

    Shada,


    I'm not sure what the problem could be. If you are able to configure all registers and see responses for both devices, it would seem that you are able to get most of this system working.

    There are two things that I think would be helpful to debugging this problem. First, can you post your command sequence with the commands and responses from the devices. I just would like to see what it is that is being sent to the device.

    Second, I'd like to check the SPI connections from the master to the device. I want to see both input and output for both devices and I'd especially like to see the output of the /DONE line from the first device to the second line. This would verify that the /DONE line is acting like a /CS to enable the SPI for the second device.

    I do have one thought that might cause this problem. After you enable the first device, the first device now expects that the ADC should be clocking out the data from all channels. Can you add 4x24 extra bits to represent the clocked out data? It could be that because the first ADC is expecting that number of extra bits, it then delays the /DONE output for the second ADC.

    Read through my comments and post back when you are able to check them all.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 110 points

    Hello Joseph,

    Thank you so much for your prompt response! 

    My problem turned out to be exactly as you described, we put the commands consecutively for both ADCs without considering the time shown from the DONE signal and that caused the command to not reach the second ADC which is why we never saw a response back. 

    We had to add filling zeros before writing the second command for device #2.

    Shada