I'm using an ADS1220 for quite time and I'm facing a really odd behavior.
- Set up ADC to continuous mode
- On falling edge DRDY interrupt trigger DMA SPI transfer for sending command and receiving data simultaneously. On DMA transfer complete I call my handler
This method worked for quite some time without observed problems. After moving some of the DMA complete processing to timer based handler things turned bad. I observed that data maintained stable for some second and then gone haywire. In some cases it stabilized within between, in other test not. After testing I thought I had the debugger identified as source of the problem. Since it may stop clocks this could cause SPI communication timeouts. So I disconnected the debugger and transferred samples over CAN bus and recorded them. During 13 hours I read some 5 million samples which were all fine.
The day after, without having changed anything, the communication didn't remain stable not even for 10 seconds. After lot of attempts to fix I identified that switching to temperature measurement and back make things start going haywire with a high probability. When letting the ADC run only in either T or input mode data readings were fine.
Now I reconfigured the ADC to single-shot mode and read samples one by one, the transmission DMA has been removed in favor of the 4 byte transmission queue in the SPI controller. Reception is still done using DMA. What can be observed now is that the byte alignment gets mixed-up. After initialization the first reading is correct. Together with the read-out (interrupt based without RDATA command while DRDY is low) is send to bytes of zero and one START/SYNC command.
Upon the next interrupt, SPI fifo is flushed before DMA setup, I get one byte added before by MSB. On the following transfer I get the LSB shifted out first followed by an 0xFF and than the MSB. Following this scheme the expected result is rotated through 24 bit.
I was not able to confirm transients on the SCLK line, especially this would be odd because why should there always be 8 addition edges to shift data? After DMA transferred 3 bytes the SPI receiver is reported empty.