Other Parts Discussed in Thread: , LMK04828, ADC32RF44
Hi,
I'm currently evaluating the ADC32RF45EVM. I had difficulties establishing a reliable link between the ADC32RF45EVM and eval FPGA boards, so I moved to a ZCU102 as I'm more comfortable starting at a low level. From another forum post I downloaded SBAA226C.zip. I'm sampling at 2949.12 MHz and I was to believe that the serdes rate should be 2.5, JESD modes 1, 1, 0 with PLL 20x.
from SBAA226C/revC/ADC32RF45/ConfigFiles_ADC32RF45_NYQUIST1/JESD_DDC_cofig_decby8_Nyq1.cfg
- register JESD 002 set to 0x01 sets JESD Mode 0 as 1
- no write to register JESD 003 defaults JESD Mode 1 as 1, Mode 2 as 0.
- JESD 037 sets PLL Mode to 20x (default)
so, jesd modes are 1, 1, 0 - pll 20x and the RX side links to a Fserdes / Fclk ratio of 2.5. The only LMFS modes ( I believe ) that has this characteristic is 8411 and found at:
- table 16. Single-Band Complex Output - Divide-by-4
- table 24. Dual-Band Real Output - Divide-by-8 (Divide-by-4 real)
From table 24, it certainly seems that either real or complex (with a divide factor of 2) is available which stands with table 16. From the jesd ddc config file listed above,
- ddc reg 001 set to 0x02 - Divide-by-8 complex
- ddc reg 002 set to 0x01 - Dual-band DDC
- ddc reg 005 set to 0x00 - Complex output format (default)
By all rights this implies that we have a divide by 8 dual band complex output in LMFS 8411. This is an 8 lane mode. However, when I look at the chip debugger ( viewing individual lanes between the PHY and the Xilinx JESD core ), I only see duplicates between lanes 0 & 1, 2 & 3, 4 & 5, 6 & 7:
I wonder if somehow this is a 4 lane mode as the active lanes in 4-lane modes are 1, 2, 5, 6. Lanes 1, 2, 5, & 6 are all at least different in the chip debugger lane data between the PHY and the JESD core.
Also, as I change to other modes (for divide by 16, etc), changing jesd/pll modes (and not forgetting 40x enable bits, etc.) I only get failures. I would like to know if there are any updated versions of these configuration codes.
TIA.
John