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ADC32RF45: SBAA226C desired behavior

Part Number: ADC32RF45
Other Parts Discussed in Thread: , LMK04828, ADC32RF44

Hi,

I'm currently evaluating the ADC32RF45EVM.  I had difficulties establishing a reliable link between the ADC32RF45EVM and eval FPGA boards, so I moved to a ZCU102 as I'm more comfortable starting at a low level.  From another forum post   I downloaded SBAA226C.zip.  I'm sampling at 2949.12 MHz and I was to believe that the serdes rate should be 2.5, JESD modes 1, 1, 0 with PLL 20x. 

from SBAA226C/revC/ADC32RF45/ConfigFiles_ADC32RF45_NYQUIST1/JESD_DDC_cofig_decby8_Nyq1.cfg

  • register JESD 002 set to 0x01 sets JESD Mode 0 as 1
  • no write to register JESD 003 defaults JESD Mode 1 as 1, Mode 2 as 0.
  • JESD 037 sets PLL Mode to 20x (default)

so, jesd modes are 1, 1, 0 - pll 20x and the RX side links to a Fserdes / Fclk ratio of 2.5.  The only LMFS modes ( I believe ) that has this characteristic is 8411 and found at:

  • table 16. Single-Band Complex Output - Divide-by-4
  • table 24. Dual-Band Real Output - Divide-by-8 (Divide-by-4 real)

From table 24, it certainly seems that either real or complex (with a divide factor of 2) is available which stands with table 16.  From the jesd ddc config file listed above,

  • ddc reg 001 set to 0x02 - Divide-by-8 complex
  • ddc reg 002 set to 0x01 - Dual-band DDC
  • ddc reg 005 set to 0x00 - Complex output format (default)

By all rights this implies that we have a divide by 8 dual band complex output in LMFS 8411.  This is an 8 lane mode.  However, when I look at the chip debugger ( viewing individual lanes between the PHY and the Xilinx JESD core ), I only see duplicates between lanes 0 & 1, 2 & 3, 4 & 5, 6 & 7:

I wonder if somehow this is a 4 lane mode as the active lanes in 4-lane modes are 1, 2, 5, 6.  Lanes 1, 2, 5, & 6 are all at least different in the chip debugger lane data between the PHY and the JESD core.

Also, as I change to other modes (for divide by 16, etc), changing jesd/pll modes (and not forgetting 40x enable bits, etc.) I only get failures.  I would like to know if there are any updated versions of these configuration codes.

TIA.

John

  • Hi John,

    The latest configuration files are available on device product page:

    I compared the config files from the old post with latest available config files on web.There are some updates. Please try with the updated files.

    Regards,

    Vijay

  • Hi The files I have are identical to these - Thanks though.

    One thing that puzzles me - The last register writes are to 0x12 to set the master page, then 0x0056 0x00 (not in documents), then 0x0057 0x00, then 0x0020 00 and 0x0020 0x10 to disable sysref.  I cannot get even the signals shown above unless I shutdown sysref on the LMK04828 (JESD just tries to sync).  I know I am writing to the ADC as the power draw changes during writes, I can reset it, etc.  But it does appear that the JESD stuff is perhaps getting written?

    I know it's aweful to look at but here is a dump of the ADC writes from parsing the config files:

    [0x00, 0x00, 0x81], adc
    [0x00, 0x11, 0xff], adc
    [0x00, 0x22, 0xc0], adc
    [0x00, 0x32, 0x80], adc
    [0x00, 0x33, 0x08], adc
    [0x00, 0x42, 0x03], adc
    [0x00, 0x43, 0x03], adc
    [0x00, 0x45, 0x58], adc
    [0x00, 0x46, 0xc4], adc
    [0x00, 0x47, 0x01], adc
    [0x00, 0x53, 0x01], adc
    [0x00, 0x54, 0x08], adc
    [0x00, 0x64, 0x05], adc
    [0x00, 0x72, 0x84], adc
    [0x00, 0x8c, 0x80], adc
    [0x00, 0x97, 0x80], adc
    [0x00, 0xf0, 0x38], adc
    [0x00, 0xf1, 0xbf], adc
    [0x00, 0x11, 0x00], adc
    [0x00, 0x12, 0x04], adc
    [0x00, 0x25, 0x01], adc
    [0x00, 0x26, 0x40], adc
    [0x00, 0x27, 0x80], adc
    [0x00, 0x29, 0x40], adc
    [0x00, 0x2a, 0x80], adc
    [0x00, 0x2c, 0x40], adc
    [0x00, 0x2d, 0x80], adc
    [0x00, 0x2f, 0x40], adc
    [0x00, 0x34, 0x01], adc
    [0x00, 0x3f, 0x01], adc
    [0x00, 0x39, 0x50], adc
    [0x00, 0x3b, 0x28], adc
    [0x00, 0x40, 0x80], adc
    [0x00, 0x42, 0x40], adc
    [0x00, 0x43, 0x80], adc
    [0x00, 0x45, 0x40], adc
    [0x00, 0x46, 0x80], adc
    [0x00, 0x48, 0x40], adc
    [0x00, 0x49, 0x80], adc
    [0x00, 0x4b, 0x40], adc
    [0x00, 0x53, 0x60], adc
    [0x00, 0x59, 0x02], adc
    [0x00, 0x5b, 0x08], adc
    [0x00, 0x5c, 0x07], adc
    [0x00, 0x57, 0x10], adc
    [0x00, 0x57, 0x18], adc
    [0x00, 0x57, 0x10], adc
    [0x00, 0x57, 0x18], adc
    [0x00, 0x57, 0x10], adc
    [0x00, 0x57, 0x00], adc
    [0x00, 0x12, 0x00], adc
    [0x00, 0x11, 0xff], adc
    [0x00, 0x83, 0x07], adc
    [0x00, 0x5c, 0x00], adc
    [0x00, 0x5c, 0x01], adc
    [0x00, 0x11, 0x00], adc
    [0x40, 0x01, 0x00], adc
    [0x40, 0x02, 0x00], adc
    [0x40, 0x03, 0x00], adc
    [0x40, 0x04, 0x61], adc
    [0x60, 0x68, 0x42], adc
    [0x40, 0x03, 0x01], adc
    [0x60, 0x68, 0x42], adc
    [0x40, 0x01, 0x00], adc
    [0x40, 0x02, 0x00], adc
    [0x40, 0x03, 0x00], adc
    [0x40, 0x04, 0x68], adc
    [0x60, 0x44, 0x01], adc
    [0x60, 0x68, 0x04], adc
    [0x60, 0xff, 0xc0], adc
    [0x60, 0xa2, 0x08], adc
    [0x60, 0xa9, 0x03], adc
    [0x60, 0xab, 0x77], adc
    [0x60, 0xac, 0x01], adc
    [0x60, 0xad, 0x77], adc
    [0x60, 0xae, 0x01], adc
    [0x60, 0x96, 0x0f], adc
    [0x60, 0x97, 0x26], adc
    [0x60, 0x8f, 0x0c], adc
    [0x60, 0x8c, 0x08], adc
    [0x60, 0x80, 0x0f], adc
    [0x60, 0x81, 0xcb], adc
    [0x60, 0x7d, 0x03], adc
    [0x60, 0x56, 0x75], adc
    [0x60, 0x57, 0x75], adc
    [0x60, 0x53, 0x00], adc
    [0x60, 0x4b, 0x03], adc
    [0x60, 0x49, 0x80], adc
    [0x60, 0x43, 0x26], adc
    [0x60, 0x5e, 0x01], adc
    [0x60, 0x42, 0x38], adc
    [0x60, 0x5a, 0x04], adc
    [0x60, 0x71, 0x20], adc
    [0x60, 0x62, 0x00], adc
    [0x60, 0x98, 0x00], adc
    [0x60, 0x99, 0x08], adc
    [0x60, 0x9c, 0x08], adc
    [0x60, 0x9d, 0x20], adc
    [0x60, 0xbe, 0x03], adc
    [0x60, 0x69, 0x00], adc
    [0x60, 0x45, 0x10], adc
    [0x60, 0x8d, 0x64], adc
    [0x60, 0x8b, 0x20], adc
    [0x60, 0x00, 0x00], adc
    [0x60, 0x00, 0x01], adc
    [0x60, 0x00, 0x00], adc
    [0x40, 0x01, 0x00], adc
    [0x40, 0x02, 0x00], adc
    [0x40, 0x03, 0x01], adc
    [0x40, 0x04, 0x68], adc
    [0x60, 0x49, 0x80], adc
    [0x60, 0x42, 0x20], adc
    [0x60, 0xa2, 0x08], adc
    [0x40, 0x03, 0x00], adc
    [0x60, 0x00, 0x00], adc
    [0x60, 0x00, 0x01], adc
    [0x60, 0x00, 0x00], adc
    ([None, None, 100], 'dly')
    [0x40, 0x03, 0x00], adc
    [0x40, 0x04, 0x20], adc
    [0x40, 0x02, 0xf8], adc
    [0x60, 0x3c, 0xf5], adc
    [0x60, 0x3d, 0x01], adc
    [0x60, 0x3e, 0xf0], adc
    [0x60, 0x3f, 0x0c], adc
    [0x60, 0x40, 0x0a], adc
    [0x60, 0x41, 0xfe], adc
    [0x60, 0x53, 0xf5], adc
    [0x60, 0x54, 0x01], adc
    [0x60, 0x55, 0xee], adc
    [0x60, 0x56, 0x0e], adc
    [0x60, 0x57, 0x0b], adc
    [0x60, 0x58, 0xfe], adc
    [0x60, 0x6a, 0xf4], adc
    [0x60, 0x6b, 0x01], adc
    [0x60, 0x6c, 0xf0], adc
    [0x60, 0x6d, 0x0b], adc
    [0x60, 0x6e, 0x09], adc
    [0x60, 0x6f, 0xfe], adc
    [0x60, 0x81, 0xf5], adc
    [0x60, 0x82, 0x01], adc
    [0x60, 0x83, 0xee], adc
    [0x60, 0x84, 0x0d], adc
    [0x60, 0x85, 0x0a], adc
    [0x60, 0x86, 0xfe], adc
    [0x60, 0x98, 0xfd], adc
    [0x60, 0x99, 0x00], adc
    [0x60, 0x9a, 0x00], adc
    [0x60, 0x9b, 0x00], adc
    [0x60, 0x9c, 0x00], adc
    [0x60, 0x9d, 0x00], adc
    [0x60, 0xaf, 0xff], adc
    [0x60, 0xb0, 0x00], adc
    [0x60, 0xb1, 0x01], adc
    [0x60, 0xb2, 0xff], adc
    [0x60, 0xb3, 0xff], adc
    [0x60, 0xb4, 0x00], adc
    [0x60, 0xc6, 0xfe], adc
    [0x60, 0xc7, 0x00], adc
    [0x60, 0xc8, 0x00], adc
    [0x60, 0xc9, 0x02], adc
    [0x60, 0xca, 0x00], adc
    [0x60, 0xcb, 0x00], adc
    [0x60, 0xdd, 0xff], adc
    [0x60, 0xde, 0x00], adc
    [0x60, 0xdf, 0x02], adc
    [0x60, 0xe0, 0x00], adc
    [0x60, 0xe1, 0xfe], adc
    [0x60, 0xe2, 0x00], adc
    [0x60, 0xf4, 0x00], adc
    [0x60, 0xf5, 0x00], adc
    [0x60, 0xfb, 0x01], adc
    [0x60, 0xfc, 0x01], adc
    [0x40, 0x03, 0x00], adc
    [0x40, 0x04, 0x20], adc
    [0x40, 0x02, 0xf9], adc
    [0x60, 0x74, 0xf4], adc
    [0x60, 0x75, 0x01], adc
    [0x60, 0x76, 0xef], adc
    [0x60, 0x77, 0x0c], adc
    [0x60, 0x78, 0x0a], adc
    [0x60, 0x79, 0xfe], adc
    [0x60, 0x8b, 0xf4], adc
    [0x60, 0x8c, 0x01], adc
    [0x60, 0x8d, 0xee], adc
    [0x60, 0x8e, 0x0d], adc
    [0x60, 0x8f, 0x0a], adc
    [0x60, 0x90, 0xfe], adc
    [0x60, 0xa2, 0xf4], adc
    [0x60, 0xa3, 0x01], adc
    [0x60, 0xa4, 0xef], adc
    [0x60, 0xa5, 0x0c], adc
    [0x60, 0xa6, 0x0a], adc
    [0x60, 0xa7, 0xfe], adc
    [0x60, 0xb9, 0xf4], adc
    [0x60, 0xba, 0x01], adc
    [0x60, 0xbb, 0xef], adc
    [0x60, 0xbc, 0x0d], adc
    [0x60, 0xbd, 0x0a], adc
    [0x60, 0xbe, 0xfe], adc
    [0x60, 0xd0, 0xff], adc
    [0x60, 0xd1, 0x00], adc
    [0x60, 0xd2, 0xff], adc
    [0x60, 0xd3, 0x01], adc
    [0x60, 0xd4, 0x00], adc
    [0x60, 0xd5, 0x00], adc
    [0x60, 0xe7, 0xff], adc
    [0x60, 0xe8, 0x00], adc
    [0x60, 0xe9, 0x01], adc
    [0x60, 0xea, 0x00], adc
    [0x60, 0xeb, 0x00], adc
    [0x60, 0xec, 0x00], adc
    [0x60, 0xfe, 0xfe], adc
    [0x60, 0xff, 0x00], adc
    [0x40, 0x02, 0xfa], adc
    [0x60, 0x00, 0xff], adc
    [0x60, 0x01, 0x02], adc
    [0x60, 0x02, 0x01], adc
    [0x60, 0x03, 0x00], adc
    [0x60, 0x15, 0xff], adc
    [0x60, 0x16, 0x00], adc
    [0x60, 0x17, 0x01], adc
    [0x60, 0x18, 0x00], adc
    [0x60, 0x19, 0xff], adc
    [0x60, 0x1a, 0x00], adc
    [0x60, 0x2c, 0x00], adc
    [0x60, 0x2d, 0x00], adc
    [0x60, 0x33, 0x01], adc
    [0x60, 0x34, 0x01], adc
    [0x40, 0x02, 0x00], adc
    [0x40, 0x03, 0x00], adc
    [0x40, 0x04, 0x68], adc
    [0x60, 0x68, 0x00], adc
    [0x00, 0x11, 0x00], adc
    [0x00, 0x12, 0x04], adc
    [0x00, 0x5c, 0x87], adc
    [0x00, 0x12, 0x00], adc
    [0x40, 0x02, 0x00], adc
    [0x40, 0x03, 0x00], adc
    [0x40, 0x04, 0x69], adc
    [0x60, 0x02, 0x01], adc
    [0x70, 0x02, 0x01], adc
    [0x60, 0x37, 0x00], adc
    [0x70, 0x37, 0x00], adc
    [0x60, 0x01, 0x80], adc
    [0x70, 0x01, 0x80], adc
    [0x60, 0x07, 0x0f], adc
    [0x70, 0x07, 0x0f], adc
    [0x50, 0x00, 0x01], adc
    [0x50, 0x01, 0x02], adc
    [0x50, 0x02, 0x01], adc
    [0x50, 0x05, 0x00], adc
    [0x50, 0x07, 0x44], adc
    [0x50, 0x08, 0x44], adc
    [0x50, 0x09, 0x9a], adc
    [0x50, 0x0a, 0x99], adc
    [0x50, 0x0b, 0xab], adc
    [0x50, 0x0c, 0x2a], adc
    [0x50, 0x0d, 0x44], adc
    [0x50, 0x0e, 0x44], adc
    [0x50, 0x1f, 0x01], adc
    [0x50, 0x14, 0x01], adc
    [0x50, 0x16, 0x01], adc
    [0x58, 0x00, 0x01], adc
    [0x58, 0x01, 0x02], adc
    [0x58, 0x02, 0x01], adc
    [0x58, 0x05, 0x00], adc
    [0x58, 0x07, 0x44], adc
    [0x58, 0x08, 0x44], adc
    [0x58, 0x09, 0x9a], adc
    [0x58, 0x0a, 0x99], adc
    [0x58, 0x0b, 0xab], adc
    [0x58, 0x0c, 0x2a], adc
    [0x58, 0x0d, 0x44], adc
    [0x58, 0x0e, 0x44], adc
    [0x58, 0x14, 0x01], adc
    [0x58, 0x16, 0x01], adc
    [0x58, 0x1f, 0x01], adc
    [0x00, 0x12, 0x04], adc
    [0x00, 0x56, 0x00], adc
    [0x00, 0x57, 0x00], adc
    [0x00, 0x20, 0x00], adc
    [0x00, 0x20, 0x10], adc

    Thanks

  • Hello,

    I wanted to add that I am able to get raw samples delivered properly using the setup I have on the ZCU102.  My lane rate is 7500Mbps, Serdes clock is 375MHz, core clock (fmc) is 187.5, and the sample clock running at 1500MHz (5x 14 bit LMFS=8224 mode) using the GUI.

    • (1) setup clock at 1500MHz, run GUI on "quick setup", bypass, 14 bit mode.
    • (2) on the LMK04828 tab, change CLKout0 divider to 4, unclick CLKout12/13 group power down, change divider to 8, DCLK to LVDS
    • (4) unclick "Invert SYNC Polarity" on ADC32RFxx/ADC Configuration tab.
    • (3) boot zcu102 and load bitstream.  reset JESD core.

    I have not been able to replicate this (at 3000 MHz) in any of the DDC modes (have tried /8 8821 dual band, and single band /16 2441)

  • Hi John,

    Can you tell the lane rates you tried with 3000 Mhz clock?

    KCU105 + ADC32RF44 Design firmware is compiled for maximum lane rate of 7.68 Gbps with 192MHz (x40) clock as the expected Reference clock form the ADC

    Regards,

    Vijay

  • Hi Vijay,

    A reminder: I'm using my own receiver on a ZCU102.

    Mine is built for 7500 Mbps and I have only been trying to use modes where the Fserdes / Fclk ratio is 2.5.  I've been running at either 2949.12 MHz or 3000 MHz.  I chose to test raw modes at 1500 MHz (Fserdes / Fclk ratio is 5) so I would not exceed 7500Mbps.

    Using the REVC zip file, parsed into Python code and the ADC configured from it, I happened to notice one time just now where the individual lanes were all different, subsequent programing has it back to the state I've mentioned previously.

    John

  • Well,

    I found that the Xilinx JESD core was behaving very strangely.  I added probes to the lines between the PHY and the JESD core and found that the individual GTs are indeed different data but the JESD core is deserializing them as shown before.  Why this did not happen in raw mode at 1500 MHz I do not know - you can see that GT0 and GT1 rxdata are different, but dbg_ln0 and dbg_ln1 are the same:

    This did not happen in raw mode.  This is part of my issue relevant to this discussion closed.  I would like to continue to work to understand why when I look at DDC data, Sysref still effects the output but not in raw mode - sysref on for ddc and the REVC config code:

    I still resort to disabling output on sysref from the LMK04828 to get a continuous stream and I suppose this may effect the JESD IP.

  • Hi John,

    Turning SYSREF off from LMK after link is established doesn't affect the JESD IP. 

    If you want to keep SYSREF continuously ON, both the below highlighted SYSREF mask bits can be set to high, ADC32RF45 should ignore the SYSREF coming in. 

    Regards,

    Vijay

  • Thanks Vijay.

    the zip file has code that manipulates "PDN SYSREF".  I will try the MASK bits instead and report back.

    thanks again

    John

  • The mask bits made no correction to my problem.  Additionally, as I've used the GUI to program the board for the raw data, I thought I'd try out a few modes.  Interesting point:  I'm trying various 2.5 Fserdes/Fclk modes and I've found that I can get nothing to work in the PLL 40x modes, but I can get some output in the 20x modes - that said, the LMFS doesn't match what I see ( L does not equal what number of lanes are deserializing data).

    All examples are Fs = 3000 MHz, Fserdes = 7500 Mbps

    "working" example 1:  LMFS = 4421 but only 2 lanes are active

    "working" example 2:  LMFS = 8224 but only 4 lanes are active

    As you can see the number of lanes as shown in the GUI are not the number I'm seeing from the PHY - only half. 

    Would it just be possible to have an engineer create .cfg files that are verified to do complex single-band DDCs on each channel A & B, decimating by 16?  I don't care too much about how to get there - I would just like a verified example, if possible.

    Thanks

  • Hi John,

    I will have to setup the ADC32RF45EVM with TSW14J56 to verify this and create a config file. I can do this early next week and get back to you.

    Regards,

    Vijay

  • Hi John,

    I have tested the DDC /8, /4 and /16 modes of ADC32RF45EVM with TSW14J56 with external 3GHz clock. I see output from both channels as expected. So I data from all lanes must be present as defined by LMFS parameters. 

    All the DDC config files used by ADC32RFxxEVM GUI can be found in the below folder on the PC with GUI installed:

    C:\Program Files (x86)\Texas Instruments\ADC32RFxx EVM GUI\Configuration Files\ADC32RFxx\DDC Mode

    The config file for decimation /16 mode is:

    ADC32RF45_DDC_16xIQ_4421.cfg

    Regards,

    Vijay