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ADS1299: Wrong my data conversion

Hidetaka Kudo
Prodigy 50 points
Part Number: ADS1299

Dear Sir,

I tried to work data conversion of ADS1299-6 using RDATAC command. But my data conversion is wrong sometimes (2300 - 2700 th data points) as the attached graph. This graph is converted the HEX value of ADS1299-6 to DEC value.

I checked the status of SPI using a simple logic analyzer, I found that the HI/LO level of DRDY was changed (HI part is shorter (LO part is longer). And I found that the HI -> LO edge timing was matched the end of SCLK, the data conversion was wrong. I do not know the reason for what occurred. 

My question is : Are DRDY HI level (3.3V) duration and LO level (0V) duration changed generally or not?

  • 0
    TI__Guru 66466 points

    Hello Kudo-san,

    Thank you for your post.

    The /DRDY falling edge indicates when new data is ready. When you read the data, the first SCLK falling edge after /DRDY will clear the /DRDY interrupt, meaning /DRDY will return high. If you never read the data, /DRDY will idle low until a few clocks before the next falling edge. Based on this description, you can see how the high and low time for /DRDY can vary depending on when you choose to read the data.

    In RDATAC mode, the new data is loaded into the output shift register automatically, indicated by the /DRDY falling edge. If the MCU is reading old data while new data arrives, the output shift register contents are immediately overwritten. You may see the /DRDY interrrupt clear immediately or you may not see /DRDY at all. This depends on the timing of /DRDY falling edge and SCLK falling edge.

    When data is overwritten in the middle of an SPI transfer, you will see corrupted data results as shown above.

    Best regards,

  • 0 in reply to Ryan Andrews
    Prodigy 50 points

    Hello Ryan-san,

    Thank you for your reply. I did not know that /DRDY would idle low until a few clocks before the next falling edge.  I understood the /DRDY behavior so I will check my source code again. 

    Regards,