ADS131A04: Conversion latency

Hao,

The ADS131A04 is able to reach 14 bits of Effective Resolution (based on RMS readings) for most data rates, however the noise is also dependent on the PGA gain, supply operation, and the reference. I would look tables 1 through 4 of the datasheet on pages 23 and 24. The data rate is listed in the second column and shows the Effective Resolution other columns for the different PGA gains. Note that there's a description of Effective Resolution on page 22.

For the conversion latency, there are two components. First, the ADS131A04 uses a sinc3 digital filter. This digital filter requires three conversions to fully settle the filter for the measurement. Additionally, there is a output buffer for the ADC data that takes one more data period to get the data from ADC to the DOUT buffer. You can think of this as four data periods of latency, or three periods of latency, but you need to wait one more period to collect the data.

Generally, I think of asynchronous interrupt mode as the standard way we collect data from the device. The /DRDY is used to indicate when data is available, and the master can collect the data after that indication. Here's a how the data path looks graphically:

For fully settled data each time, you could collect data one of two ways:

1. Wait 4 /DRDY periods and only collect the 4th data.

2. Wait for groups of 3 /DRDY periods, and wait one more data period to collect the data

Regardless, if the desired overall data rate is 300Hz, the ADC should be able to collect settled data at OSR settings as high as 2048 (2kHz for fDATA).

Joseph Wu