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ADS8684A: REFIO/REFCAP cap layout path

Zoe Ko
Expert 3830 points
Part Number: ADS8684A

Hi team,

From the datasheet we know that the caps for REFIO and REFCAP to REFGND should be put close to the pins.

If we would like to quantify the layout path for REFIO and REFCAP to REFGND, could you please help let us know no more than how long(mils) and do you have some standard?   

Thank you!

  • 0
    TI__Mastermind 45865 points

    Hi Zoe,

    There is no standard for such layout also it's hard to say how long the trace should be limited to. However, below is the guideline for the layout regarding REFIO and REFCAP:

    1. The capacitors should be as close to REFIO/REFCAP pins as they can, see the board layout recommendation shown in Figure 128 of datasheet (22uF+1uF capacitors between REFCAP and REFGND,a 10uF capacitor between REFIO and REFGND). Also, below is the layout on ADS8688EVM, the capacitors C9 and C12 between REFCAP (pin7) and REFGND (pin6), C7 is 10uF capacitor on REFIO (pin5). They are close the ADC U2.
    2. The reference signal (REFIN) should go through C7 capacitor firstly before applying to the REFIO pin 5. Please see the EVM layout below.

    I hope these information are helpful to you.

    Thanks&regards,

    Dale