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ADS8319: question regarding tACQ

Ue
Genius 16295 points
Part Number: ADS8319

Hi all

My customer is using the ADS8319 and he has below question.

Please comment and clarify.

Thank you and best regards

Ueli

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I have some difficulties in correlating the information from Table in datasheet chapter 7.6 against Figure 50 (which describes the 3-Wire CS Mode Without Busy Indicator operating mode, which is what we want to use).

 Particularly, I have difficulties in understanding the tACQ minimum 600ns value.

 Judging by Figure 50, we need to provide 16 clock cycles. The table in question indicates the minimum clock period (tCLK) as being 20ns, so this means to 16 clocks would take 320ns. In addition, we need to consider the ten and tdis values described in the picture, which the table indicates as being 15ns and 12ns, respectively. If I add all these, then I end up with a total of 347ns, and I cannot corelate this with tACQ.

 The plan is to keep the CONVST pin high for 1400ns and once we bring it down we would immediately launch the SPI clock(after waiting ten), so a whole cycle would last 1400ns + 347ns = 1747ns. Do we need to delay the start of the next conversion? Or do we need to delay the SPI clocks relative to the falling edge of CONVST (or the end of tcnv, maybe…)?

 

  • 0
    TI__Mastermind 36710 points

    Hi Ueli,

    There is no maximum time that CONVST can remain low.  If you run SCLK at the highest rate possible, as in the above example, you would simply keep CONVST low after the 16th SCLK until a minimum of 600nS has elapsed.  SDO goes to hi-z state after the 16th falling edge of SCLK and will remain in this state until the next falling edge of CONVST.  Since you are keeping CONVST high for the maximum conversion time of 1400nS, you will have a total of 600nS to clock the result out.  In this case, allowing for ten and tdis, you can run SCLK as low as (600-15-12)/16=36nS, or 27.8MHz and still maintain the maximum data rate of 500ksps.

    Alternatively, there is no maximum time that CONVST can remain high.  Since the conversion time is controlled by an internal clock to the ADC, you could keep CONVST high for 1400nS+253nS, and then take it low for 347nS, to keep the total minimum cycle time at 2000nS.  However, this option is not preferable since you must run SCLK at the maximum possible speed in order to sample data at 500ksps.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Genius 16295 points

    Hi Keith

    Very good, thank you for the quick reply !

    Best regards

    Ueli