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DAC7734: VOUT level during power-on.

ttd
Mastermind 7790 points
Part Number: DAC7734
Other Parts Discussed in Thread: DAC7744

Dear Technical Support Team,

I have a question about Vout level during power-on.

According to the data sheet,  voltage level of RESTSEL when RST is rising edge, it sets zero scale or middle scale value.

During power-on, before  both RST rising  and  RESTSEL value latched, what is the scale value for VOUT output?

Best Regards,

ttd

  • 0
    TI__Mastermind 18776 points

    Hi,

    Following is my understanding of DAC7734 from datasheet.

    Since this part has internal Power On Reset (POR) circuit which is triggered on VDD, you dont need to give any explicit RST SIGNAL. Also POR is gated with RESTSEL, what this means is that, when you are in during power on state before RST and RESETSEL being latched , it can be in any state since RESETSEL state is unknown (my understanding, needs to check with team)

    I am not sure of the output state until RESETSEL is latched. I will revert back after checking with my design team.

    How is your power up sequence? VDD comes along with RESETSEL or RESETSEL is at fixed logic level?

    Since these are very old parts, I suggest moving to a new part from our DAC family.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    TI__Mastermind 18776 points

    Hi,

    Both the POR as well as a rising edge on the RST pin will cause a low level reset pulse to the DAC register. The internal RESET signal as shown in attached schematic dac7744_2 goes to a bank of flip flop or latches and connects to their individual clear pin.  For the MSB latch or flip-flop, there is some simple decoding logic of the RSTSEL value and the MSB latch or FF has both a set and clear pin.  Depending on the state of RSTSEL, this MSB latch/FF will either be set high or low depending on the state of RSTSEL.  As long as RSTSEL is at its proper value about 10ns before the end of the internal RESET signal it will be set to the desired RSTSEL state.  If RSTSEL is initially zero, then the latch/FF will initially be set to zero, but assuming RSTSEL changes at least 10ns prior to the internal RESET going high, it will ultimately follow the RSTSEL state.

    As for the DAC output on power-on, note that these old devices did not have any power-on glitch reduction circuitry at all. Thus we never really measured it or even tried to eliminate it.  Since State RSTSEL is unknown during power on, there can be output glitches beyond midscale or zero scale.

    I would strongly recommend RSTSEL tie to ground or supply (5V) for known state during power on rather than bring it up along with supply lines.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Mastermind 7790 points

    Hi AK,

    Thank you for your reply.

    >attached schematic dac7744_2 

    Did you attach the file such as pdf or PPT?

    It seems that the file wan't attached on your post.

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Mastermind 18776 points

    Hi ttd,

    I didn't attach anything on this post. That's an internal schematic of the device which I cannot share.

    Hopefully you understood device behavior from my earlier post.

    Let me know if you have any more concerns regarding the same.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Mastermind 7790 points

    Hi AK,

    Thank you for your quick reply.

    I understand that you can't attach the internal circuit.

    In my case, RESTSEL is fixed GND (low level).

    RST signal is asserted from FPGA. The sequence of power-on is below.

     

    At first, After power-on, FPGA keeps RST low level with internal pull-down resistor until boot is completed.

    Secondly, RESTSEL(GND / Low level) is latches by rising edge of RST after FPGA boot, it becomes zero scale value.

     

    According to your comment,

    ”Since State RSTSEL is unknown during power on, there can be output glitches beyond midscale or zero scale.”

    Is there output glitches beyond zero scale while FPGA is booting(before RESTSSEL is latched)?

     

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Mastermind 18776 points

    Hi ttd,

    There can be output glitches at power on beyond zero scale before the state of RSTSEL is latched. Since this very, very old (From Burr Brown time), we didn't characterize extensively power on output glitch at these conditions. I think in those days this was not a concern and didn't impose anything on design conditions.

    Given these limitations, I suggest have appropriate output clamp circuit for protection to following stages.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Mastermind 7790 points

    Hi AK,

    Thank you for your reply.

    I understand that output should be glitches  during power-on.

    By the way, I have a question about below.

    >I would strongly recommend RSTSEL tie to ground or supply (5V) for known state during power on rather than bring it up along with supply lines.

    When RSTSEL tie to supply (5V)  for known state during power on, I think  that it exceeds the absolute max below.

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Mastermind 18776 points

    Hi,

    what I meant by this is do not control those lines with some MCU or processor. If your power supply (VDD) , tie to that  or connect to GND. This way you are not going to violate any conditions.

    Hope this clarifies.

    Regards,

    AK