Hi,
I would like to calculate the deterministic latency between the sample instance and the data available in the FPGA. There is not much in the data sheet for this issue. I found the values t_ADC and t_TX on page 24. A Xilinx FPGA with GTH transceivers is on the reception side. I found TI articles describing an approach but they use timing parameters (t_TXLMFC) not available for the ADC12DJ3200 device:
e2e.ti.com/.../jesd204b-how-to-calculate-your-deterministic-latency
Anyone an idea? Thanks in advance.
Best regards
