1) With respect to BVdd being applied before Dvdd and AVdd, what is the expected failure in this condition? Is it resolved by a hardware or software reset?
2) With respect to the assertion of the nSS pin during power up of the device, what is the expected failure in this condition? Is it resolved by a hardware or software reset? Is it resolved by doing an initial read of the DAC input shift register to clear the buffer? From page 36 in the AMC7823 data sheet Rev E.
Thanks,
Peter
