Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 163 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC8560: sample rate

Yuto Sakai
Mastermind 6100 points
Part Number: DAC8560

Hi,

Could you tell me the sampling rate of DAC8560?
There is no spec in the data sheet.
Also, is an anti-aliasing filter required for external circuits?

Best regards,
Yuto Sakai

  • 0
    TI__Mastermind 18996 points

    Hi Sakai,

    You can calculate DAC8560 update/sample rate as follows. From datasheet for VDD= 3.6 V to 5.5 V, calculation goes like following.

    Update rate  = (SCLK cycle time)*24 + SYNC to SCLK rising edge setup time + Data setup time + Data hold time + Min Sync High Time  +  Output Settling Time

    Update rate  = (50ns) *24 + 0ns + 5ns + 4.5ns + 33ns + 12us (case for RL  =2K and CL = 500pF)

    Update rate  = 13.252 us.

    Please note that in this case your output voltage settling time dictates your update rate mostly because interface parameters are negligible.

    Similarly you can calculate for other power supply conditions as well.

    Remember output voltage settling time is a function of load capacitance and code step, we have characterised this number with 500pF load capacitance.

    Regards,

    AK