Hello,
we asked for help with understanding impedance of ADS52J65s analog input month ago (https://e2e.ti.com/support/data-converters/f/73/t/871712). You provided impedance model of analog input but unfornately we have to resume to this topic.
Provided model was used to design the front-end what does impedance matching at specific frequency bandwidth and decreases the full-scale of the ADc without significant degradation its SNR. It seems the provided model is not usable after our measurements.
The model can be simplified to parallel RC represantion - circa 1.7kOhm || 7pF. So the impedance should have capacitive character what should change +/-2pF based on input frequency. Results from our observations show that R representation (real part) is probably OK. Problem is with the imaginary part where we are facing strange behaviour.
We have tried by trial and error specify the imaginary character of input impedance. This was done by using front-end with 1:4 transformer (transformation 50ohm->200ohm), increasing the differential resistors from 50ohm to 240ohm (240 || 1.7k = 210) and placing parallel inductor to input. This is known technique to design band-pass impedance matching front-end to ADC described in AN-935.
With the changing value of the inductor we tried to find the capacitance value of internal impedance - by observing LC resonance with vector analyzer and from power-gain plot from ADc data output. Theoretically increasing L value should decrease LC resonance (bandpass filter) value. Our measurements shows that the frequency position of the pit of S11 (return loss) decreases with higher inductor what is expected behaviour.
Problem is with the "S21" or power-gain obtained from ADc output where dBFS amplitude versus input frequency is observed. The peak of the S21 transmission is stucked at 110-120MHz. It seems the rf signal is not properly delivered into ADc. We suspect the ADc input impedance have not stable imaginary character (capacitive reactance). This doesn't correspond to provided model or behaviour of other ADCs with switched-capacitor architecture.
We believe we need more help and information about ADS52J65s analog inputs. Otherwise we (or other users) won't be able to design proper analog front-end to ADS52J65 inputs.
Can you please help us?
Thanks and regards,
Daniel
