Part Number: ADC32RF42
Other Parts Discussed in Thread: ADC12QJ1600
Hello,
please how is ADC sampling done? It is not in datasheet!
Triggered by CLKIN? On which edge?:
- rising
- falling
- both (like DDR)
In block diagram is a clock divider /4. Does it affect JESD204B or triggering too?
If I need 1,5GSPS, what frequency should be put to CLKINp/CLKINn pins?:
- 0,75 GHz
- 1,5 GHz
- 6 GHz?
I need to synchronize sampling moment of 8 of those ADCs (=16 analog channels).
Thanks a lot for help.
Hi user,
To operate at 1.5GSPS, input clock frequency should be 1.5GHz. Each ADC channel is internally interleaved two times. So there is a divide-by-2 clock divider to provide clocks to individual ADC cores. The block diagram in datasheet mistakenly shows it as divide-by-4.
In ADC32Rf42, multi-device synchronization is achieved by using external SYSREF signal which is used to align all internal clock phases and the local multi-frame clock to a specific sampling clock edge. This alignment allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty.
As this application needs 16 channels, I suggest using TI's latest quad channel ADC, ADC12QJ1600 
Regards,
Vijay
