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ADS127L01EVM: SPI Chip Select operation

David Bristow
Prodigy 60 points

Part Number: ADS127L01EVM

I am using the ADS127L01EVM with some additional logic to generate a pulse signal synchronized with the ADC sampling that acts on the test circuit generating the signal the ADC is sampling. Using a logic analyzer I found that the chip select signal on the J6 DEBUG header was active while the ADS127L01EVM was idling and then changed to a shorter signal during acquisitions. That allowed me to keep my test circuit synchronized even when I wasn't recording data. Something happened and now the chip select signal is active only when data are being recorded. Is the latter case the expected case, or did I somehow or other change the operation of the board so that chip select is active only when data are being recorded?

  • 0
    TI__Guru 68966 points

    Hi David,

    Thank you for your post.

    Are you using the provided Delta-Sigma EvaluaTIon GUI and MCU firmware as-is? I'm not entirely sure if by "additional logic" whether you've attempted to modify the source code or not. 

    The firmware may have been polling the register settings periodically when data was not being captured. I believe the firmware developer did this to ensure that any changes to the hardware mode pins were updated in the MODE register (07h) in the GUI's register map. The SCLK frequency was run at 200 kHz during simple register reads, which explains why the /CS-low duration was longer compared to data acquisition mode. Perhaps when you made some changes, the polling function stopped working, which is not a huge deal as long as the register map in the GUI reflects the current device settings.

    The fact that you are still able to capture data reliably tells me that nothing is broken with the hardware or software yet. 

    Best regards,