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ADS54J60: ADS54J60 SPI communication issue

Gary Beck
Prodigy 190 points
Part Number: ADS54J60
Other Parts Discussed in Thread: LMK04828,

Have 3rd party custom hardware with a LMK04828 used to source the device and SYSREF clocks for a ADS54J60.  Having troubles with SPI communication.  Following the initialization sequence as noted in table 75 with one notable difference.  The hardware reset does not comply with the datasheet.  The reset pin starts to go high with the power supplies ramping up then goes low before the supplies reach their nominal voltage.  Guessing the invalid hardware reset may be causing the SPI communication issue. 

Is the write of address 0x0000 to 0x81 truly an equivalent to a hardware reset?

Regards, Gary

  • 0
    TI__Guru* 91947 points

    Gary,

    No. The external reset does every internal register. The soft reset does not. But this may not be your problem. For the SPI to work the sample clock must be present and the SPI clock can be no faster than this frequency / 500. If you are using a 1GHz sample clock, the max SPI clock can be is 2MHz. See section 8.4.1.1 for more information regarding this.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 190 points

    Jim,

    Thanks for thre quick reply!  Since the hardware reset isn't valid it seems we can't rely on the reset default for any register. 

    However it sounds like the our SPI clock frequency (1.5MHz) is the SPI communications issue.  The CLKIN frequency is 400MHz.  The FPGA is being recompiled to use a SPI clock of ~0.5MHz.  Hopefully this fixes the issue.  Will let you know.

    Thanks, Gary

  • 0 in reply to Gary Beck
    Prodigy 190 points

    Jim,

    Slowing down the SPI clock resolved our communication issue.  Thanks for the help.

    Regards, Gary