ADS1262: No DRDY pulse on power up and no SPI response

Hi pa,

Welcome to the TI E2E Forums!

How are the AVDD and AVSS supplies being generated, and are they referenced to the same ground plane as DGND? If you have a more complete schematic that you can share it would be helpful (you can email it to pa_deltasigma_apps@ti.com if you prefer not to attach it to this thread).

From your info, it looks like the "AVDD - AVSS" supply voltage is a little low (4.5V; minimum recommended analog supply voltage is is 4.75V). Also, REFOUT should have a voltage potential of AVSS + 2.5V, which might indicate that there is a bad connection somewhere.

Hi Chris,

Thank you for the brief repply. I've sent you a complete schematic fo the device via email.

Power supply reails are generated by TI LM27762DSSR dual power supply + LDO chip. I designed it to deliver +/-2.5V of supply for AVDD and AVSS, but indeed I see some soldering issues all over the board. Maybe I'll inspect this more thoroughly and get back with the findings ASAP.

Hi pa,

Thanks for the schematic!

Nothing stood out to be as a major problem. One minor issue I spotted was that the LM27762DSSR, which is generating the +/-2.5V analog power supplies is biased with respect to the digital ground, and as such all of this power supply's return currents will have to flow through the jumper back to digital ground. Hopefully this return path is short and low impedance, but it would be better to bias LM27762DSSR with respect to the analog ground.

...Even better yet, would be to have a single ground plane, as I wrote up in the following E2E FAQ:  [FAQ] PCB Layout Guidelines and Grounding Recommendations for High-Resolution ADCs. However, you might say I'm a little bit "biased" on this topic. ;)

Hi Chris,

Thank you for the review of my schematic. Indeed, there's nothing wrong with it. I think I've found the issue, but not the solution so far. On page 6 of the datasheet there's a remark that input pins are diode-clamped to analog supply rails. The thing is that my detector arrays are sometimes overdriving the inputs.

I have an array of photodiodes with transimpedance amplifiers powered with an external 0-5V power supply. Under normal circumstances diodes work in a fairly dark environment and the output of their op-amps never exceed +1V. But when exposed to ambient light conditions (which is the case during an assembly process etc), the output of transimpedance amplifier is saturated (+5V). This causes ADS1262 to clamp, power source goes crazy and bad things happen.

Below is an outline of the detector schematic.

Do you have an idea of how to handle this special conditions while trying to maintain as much of the dynamic range of the ADC as possible? I think the problem is with a proper signal conditioning stage. The signal of the detector is unipolar positive voltage that oscillates between 0 and 200 mV and occasionally goes beyond that to say +1V with some extreme conditions when the output saturates to +5V. Now the PGA of ADS1262 handles the most of the signal conditions (thus using only half of the positive voltage range), but during the overvoltage states the circuit becomes unstable.

Pa,

I saw your post and just thought I would attach a document on photodiode amplifier noise.  I'm not saying you have an issue, but I know that it can be challenging to keep these amplifiers stable.  I hope the attachments are helpful.

3833.noise11-Photodiode-Noise 1.pdf

6242.noise12-Photodiode-Noise 2.pdf