This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12DJ3200EVM: Reference design for ADC12DJ3200EVM & Xilinx

Part Number: ADC12DJ3200EVM

Hello,

My name is Elad Levy, and Im a system engineer at a consulting company called ArcYtec.

Im interested in purchasing the ADC12DJ3200EVM but I would like to know if I can get a reference design to the KC705 Xilinx evaluation board?

I saw on the web that there is reference design for the KCU105 Xilinx EVB but I already have the KC705 so I would very much like to use it instead of buying a new EVB.

  • Elad,

    The KC705 only has 4 RX serdes lanes routed. The ADC12DJ3200EVM routes DA0-DA3 to these lanes. With this, you will only be able to operate with JMODE15 (single lane). Is this an issue for you?

    Currently we do not have a reference design with this ADC but have one for a couple of our other ADC's. This reference design can be found under the TSW14J10EVM product folder on the TI website. 

    Regards,

    Jim  

  • Hi Jim, thanks for the quick reply.

    I think its OK.. I only need to sample one differential signal @3.6GHz (12bit).

    According to what you wrote it should be OK is it not..?

  • Elad,

    As long as you need complex data, 15-bit and decimate by 16, then you are OK.

    Regards,

    Jim