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ADS8588H: BUSY SIGNAL NOT GOING HIGH IN SERIAL AS WELL AS PARALLEL MODE INTERFACE CONNECTED TO THE FPGA

Part Number: ADS8588H

I am giving the conva and convb signal as per the timing requirement in the datasheet ,even though the busy signal is not going high. 

  • Kabilan,

    1.  A scope or logic analyzer picture would be very helpful for debug here.

    2. Are you using serial or parallel communications?

    3.  Are you using the method described in figure 67 or 68?

    4. FYI.  The EVM can be used as a reference design. Do you have an EVM?

    Looking forward to the additional information.  Good luck with the debug.

  • Attached the Screeshot of the analyser.

    using parallel mode to read data.

    using figure 68.

    don't have an EVM.

    thanks you

    K.Kabilan.

  • Kabilan, 

    Can you help me to understand the meaning of the different signals?  If the signal doesn't pertain to the ADC just let me know that.  By looking at the screen shot, I wonder if any of the ADC digital outputs are responding to the digital inputs.  I notice that CHANNEL1, BUSY, and FRSTDATA are all at a static logic level.  If no digital output is changing, I think we better check the wiring of the device.  Check each supply, confirm grounds, check the reference . 

    Also, how many prototypes have you built?  Perhaps the device was damaged during debug or assembly.  The bottom line is that you will normally see some change in the digital outputs if you are wired correctly and the part has not been damaged.

    I hope this helps.  Best regards,