From the Figure 4−15 "THS8200 DTG VS/HS Output Generation" in the THS8200 datasheet, HS_OUT and VS_OUT are basically generated when pixel and line counters (respectively) expire after being reset by input sync signals (HS_IN, VS_IN and FID when not embedded in datastream).
However this seems to imply that the alignment of HS_OUT and VS_OUT does not depend on whether it is Field1 or Field2 when set up for interlaced output, which would make it very difficult to determine odd/even fields, since there is no FID_OUT pin.
Normally when FID is not available, VS and HS will be aligned in Field2 and not aligned in Field1. Is this the case for the THS8200?
