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DAC1220: What is the maximum Data Rate (Sampling Rate) in DAC chips ?

Simon Burkhardt
Prodigy 10 points
Part Number: DAC1220

I am currently looking the datasheets of different DAC parts. (e.g. DAC1220)

However, I cannot seem to find a parameter that specifies the maximum data rate comparable to the sampling rate in ADCs.

How is this data rate given? I know that the settling time limits the bandwidth of the output signal, but is this also the maximum rate at which the DAC processes the digital signal?

Would the following be an approach to get the maximum data rate?

f_s = f_sck / N

where f_sck is the SPI master clock and N the resolution in bits.

  • 0
    TI__Mastermind 19086 points

    Hi Simon,

    There is subtle difference between settling time and update rate of a DAC. Generally speaking for a DAC,,your update rate predominantly dominated by settling time, since your interface speeds (SPI) are much higher. 

    Update rate =  Settling time  + Interface timing parameters, lets say a  20bit DAC, and operating with 50MHz clock and having a settling time of 1us, your update rate will be roughly equals to 1us  + 20ns*20  + CS going low to SCLK rise or fall time (assuming 5ns) + SCLK fall edge or rise edge to CS going high (5ns).

    which equals  1.410us.

    In case of DAC1220, settling time is 15ms which will dominate your update rate if you are looking at 20bit mode of operation. Plus additional interface timings you need to add depends on what clock rate you are operating. 

    Below is our Precision DAC training series which talks about update rate in DAC .

    https://training.ti.com/lessons-precision-dacs-settling-time-vs-update-rate

    Regards,

    AK