ADS5263: ADS5263IRGCT- ADC Pace Errors

Lauren Haskin

Part Number: ADS5263

Currently seeing Trigger 23 - ADC Pace Errors in our system related to the TI part ADS5263IRGCT. These chips are dependent on timing and it fails in the transition phase when the temp changes (i.e going from hot to cold or vice versa). Are the parameters inside of the chip determined by temp? Looking for input/feedback from TI on these failures.

over 5 years ago

0 Chen Kung over 5 years ago

TI__Genius 12025 points

Hi,

Thanks for using ADS5263 devices.

I will report your question to our manager and will let you know soon.

Thank you!

Best regards,

Chen

0 Chen Kung over 5 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi,

When the temp is changed, the FPGA needs to do the dynamic phase alignment for LVDS timing.

Please consider this issue.

Thank you!

Best regards,

Chen

0 Lauren Haskin over 5 years ago in reply to Chen Kung

Prodigy 90 points

Thanks. We would really like to have a discussion with our team of design engineers to discuss this further. Please provide a number /name that can be reached.

0 Lauren Haskin over 5 years ago in reply to Chen Kung

Prodigy 90 points

Hi Chen,

This would be true if we were getting LVDS errors, but we aren’t. We aren’t having any issues with the LVDS timing. So, this doesn’t really answer our question.

But, I’m also not sure the question accurately reflects the issue we are having. Essentially, TI needs to know that as we transition across temperature, the output BIT clock is slowing down for a period of ~200 ns, before going back to full-speed. However, the input clock is not changing.

We would like to have a call to discuss. Please help to provide a contact # that I can call.

Thanks,

Lauren

0 Chen Kung over 5 years ago in reply to Lauren Haskin

TI__Genius 12025 points

Hi,

If your FPGA double confirm does not help your cold temp condition,

then could you please refer to ADS5263 data sheet page 10

about the Programmable LCLK Phase

more detail settings on Page 44

1) Set register 0x42, set register bit EN_REG_42 = '1'

2) Set register 0x42, set PHASE_DDR<1:0> 2bits as '10' default mode value.

Hope this can help.

Thank you!

0 Chen Kung over 5 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi,

Also could you please provide the followings to us:

===================

show a picture or so.

If it is one bit clock, it is only a glitch.

If it happens all the time, then it will be the issue.

====================

0 Lauren Haskin over 5 years ago in reply to Chen Kung

Prodigy 90 points

Hi Chen,

We have confidential information that we cannot share over the internet. We really need to discuss over a conference call as this chat is not a sufficient platform. Please help to provide a contact # so that a conference call can be set up.

0 Chen Kung over 5 years ago in reply to Lauren Haskin

TI__Genius 12025 points

Hi,

Please send information to

mysecuresoftware_medical@list.ti.com - contact for my secure software requests

then we also can discuss your request.

Thank you!

0 Lauren Haskin over 5 years ago in reply to Chen Kung

Prodigy 90 points

Hi Chen,

If ’10’ is the default value for the PHASE_DDR, do we need to write to the register? We are currently not writing anything to that register.

Thanks,

Lauren

0 Chen Kung over 5 years ago in reply to Lauren Haskin

TI__Genius 12025 points

Hi,

The default value of <PHASE_DDR> bit = 10.

For normal condition such as room temp, its register value should be in the default condition.

But you can force it into a forced condition, then if this is the issue caused by the temp changed

it will stay the same value.

=============

Notice: please in this case, also need to set <EN_REG_42> = 1

D15 <EN_REG_42>
0 Disables register bits D6, D5 and D3
1 Enables register bits D6, D5 and D3

=============

Thank you!

Best regards,

Chen

0 Lauren Haskin over 5 years ago in reply to Chen Kung

Prodigy 90 points

Hello,

We ran the test with the new firmware that writes to the register like TI suggested. We still got the pace error, so writing to the register didn’t help. We are still seeing the issue.

Thanks,

Lauren

0 Chen Kung over 5 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi,

could you let us know how to cal?l; then we can have discussion with them directly.

Thank you!

Have a nice day!

Best regards,

Chen

0 Chen Kung over 5 years ago in reply to Chen Kung

TI__Genius 12025 points

Hi,

Please send information to

mysecuresoftware_medical@list.ti.com - contact for my secure software requests

then we also can discuss your request.

Thank you!

0 Lauren Haskin over 5 years ago in reply to Chen Kung

Prodigy 90 points

Great! what day and time works best for the meeting? I can send you the call-in information after you confirm.

0 Lauren Haskin over 5 years ago in reply to Lauren Haskin

Prodigy 90 points

Let me know if Monday May18th at 2pm EST / 6pm Your time works.

0 Chen Kung over 5 years ago in reply to Lauren Haskin

TI__Genius 12025 points

Hi,

Can you please request to set up as Monday EST 2:30pm, or Dallas time 1:30pm?

Thank you!

Have a nice day!

Best regards,

Chen

0 Lauren Haskin over 5 years ago in reply to Chen Kung

Prodigy 90 points

Great. Done I have sent the call-in information to your secure email. It is scheduled for Monday EST 230pm

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ADS5263: ADS5263IRGCT- ADC Pace Errors