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TSW14J56EVM: A question about "bin_ch_data" input port.

Fernando Sanz
Prodigy 240 points

Part Number: TSW14J56EVM

Dear all,

Hi,

I am using TSW14J56EVM with ADC34J45EVM.

I'm going to do some DSP operation and filtering on the raw data.

There is an input port at the top-level design ( [15:0] bin_ch_data ). Is this the decoded data achieved by ADC and transmitted through jesd204b?

Since the ADC is 14 bit, I wonder which is the signed bit in this data? 14th or 16th bit?

unfortunately, I couldn't simulate the design successfully but it is important for me to know the true format of the bin_ch_data input port at the top-level design.

Thanks.

Fernando.

  • 0
    TI__Guru* 91947 points

    Fernando,

    We are looking into this.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Guru* 91947 points

    Fernando,

    No, bin_ch_data[15:0] is not ADC decoded data. In the TSW14J56EVM firmware FW, the bin_ch_data[15:0] inout port is enabled for DAC when binary channel mode (BCM) is enabled in HSDC Pro INI file.

     

    The ADC raw data form JESD block can be obtained by probing the jesd204_rx_link_data from JESD Base IP in jesd_rx_top  module in FW. The TSW14J56EVM firmware released online is compiled for 8 Lane mode where the jesd204_rx_link_data  contains 256 bits of JESD Rx parallel data (32 bits from each lane).

     

    The targeted ADC34J45 operates in 4L or 2L modes. HSDC pro will reconfigures the FW for the respective modes based on the INI file selected.

    Note: you can also manually reconfigure the JESD Base IP parameters (LMFSHd) along with other FW modules to your targeted JMODE.

     

    Please refer the ADC34J45 Datasheet to understand more on targeted JMODE to get signed MSB bit.

     

    Regards,

     

    Jim