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ADS127L01: In 64 K Sampling, It only receives 63999 data per second.

soonho lee
Prodigy 10 points
Part Number: ADS127L01

HI,supporter

Now i am used the ADS127L01 in my project. 

In 64 K Sampling, It only receives 63999 data per second.

when I check the DRDY's Falling Edge and next Falling Edge, Mostly 15.625us but 15.650us is sometimes. (About 435 out of 64000) 

My FPGA is 40Mhz. so 25ns is Tick time.

What does this happen?

  • 0
    TI__Guru 66346 points

    Hello Soonho,

    Thank you for your post and welcome to our forum!

    The period between /DRDY should be exactly the same number of CLK periods per sample. It takes an exact number of master clock rising/falling edges for the internal state machine to complete a conversion. One possibility is that there is some noise on your clock signal which is being interpreted as an extra clock edge. Can you try slewing the clock input with a small 10-pF cap to DGND?

    How are you measuring the /DRDY period?

    Best regards,