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ADS7951 measurement errors

Other Parts Discussed in Thread: ADS7951, ADS7891

Hello,

I'm coping with a problem concerning A/D measurements done with the AD-converter ADS7951.

At first I'll describe the application it is used in: this is an high power inverter (~15kW) where the ADC converts the measured voltage values of the IGBT-temperature NTC, the divided down input voltage (up to 400V) and the divided down phase to phase voltage. In low power mode the reported measurement values are correct. At 400V input voltage and full output load the converted values are faulty. There are positive or negative distortions on either one or multiple channels. The idea was that the measurements were done in a switching moment. So the approach to solving the problem was to shift the measurement into a gap where there is no switching of the IGBTs (falling edge of chip select is at the start of the gap). But this did not help.

So one first question is if somebody had a similar problem before.

Up to now, the opinion was that the channel to convert is chosen at a falling edge of the chip select (CS) signal. But in the data sheet on page 23 it is described in a different way. There it says: "the acquisition phase starts on the 14th SCLK rising edge. On the next CS falling edge the acquisition phase will end, and the device starts a new frame." So this would mean that there is a very long acquisition time. This could explain why the solution described above did not work. Is the acquisition phase (channel connected to the internal capacitor, compare figure 59 on data sheet) really this long?

Is the defined over voltage recovery time of 150ns (specified in electrical characteristics on page 7) valid for all voltages (there is no condition specified)?

I'm looking forward to answers!

Thanks and best regards,

T. Abele

  • Hello Tobias,

    It appears that you are sampling three different voltages on different channels of the ADS7951.  Are you getting incorrect measurements for all of the channels or only for the divided down input voltage?

    Regarding part operation, when chip select (CS) goes low the conversion phase begins. This conversion is the data acquired in the last frame. During each frame you also configure the next channel to sample (in manual mode) and this channel is acquired in the next frame, and its data is converted in the following frame.

     

    The acquisition phase must be at least 325ns long. It begins on the 14th SCLK falling edge in a frame and ends once CS goes low again (the end of the frame). Be sure to take note of the application note on page 40-41 of the ADS7951 Datasheet that describes some drive/buffer circuitry options. A longer aquisition time ensures that the internal sampling capacitor charges up to a more accurate value (closer to the final value).

    Overvoltage recovery time applies to input voltages that exceed the "Absolute input range" (either -0.2V to Vref+0.2V or -0.2V to 2*Vref+0.2V, depending on which range you select).

    Other information you could provide me that would be useful to help me assist you would be the input voltages you are using (the range of voltages you are sampling, the analog supply voltage, the digital supply voltage and the reference voltage). Also knowing what the output conversion results you're getting versus your expected results might help!

    Best regards,
    Chris

  • Hello Chris,

    thanks for your reply! At first an image with the output conversion results at 400V input voltage and an RL-load. In this image, the measurement takes place in a none switching moment. The peaks here are on the divided input voltage (lighter green) and on the divided output phase to phase voltage (darker green). But dependant on the sampling moment (falling CS edge) and the modulation index there are also or only such peaks on the temperature channel (blue). The measured values besides the peaks are correct. 

     

    The input voltages are: 0-5V for temperature measurement (Ch2), 0-5V for input voltage measurement (Ch3) and 0,5-4,5V on phase-to-phase voltage (Ch4) measurement. The analog and digital supply voltages are both 5V and the reference voltage is 2,5V.

    Best regards,

    Tobias

  • Tobias,

     

    Thanks for the screenshot.  I wasn’t able to see all the details, but I am curious what your sampling rate is and how your cycling through the different channels. It appears like only one point is sampled on each peak and that the peaks are cyclical. What values are you expecting instead of the peaks shown in your image? It is possible that the ADS7951 is cycling through channels that you’re not using or not interested in? (You mentioned your inputs are connected to channels 2, 3 & 4; what is connected to channels 0,1,5,6 & 7? Is the part operating in one of the automatic sequencing modes?)

     

    Would you be willing to attach a schematic, showing how the ADS7951 is used in your application? This is a new application for me and I appreciate the extra information so I can do my best to help you.

     

    Best regards,

    Chris

     

     

  • Hey Chris,

    thanks for your answer. The peak values are totally wrong, I expect the same values like on the peak's left and right. But the reported values are correct (no peaks) if there is no PWM on the IGBT gates or if the input voltage is below a certain point. So the circuit should be correct. The not used channels are connected to Gnd with a 1k resistor.

    The error pattern is not always the same. The peaks are changing amplitude/frequency with rising input voltage or change of PWM modulation index.

    Here a screenshot of yesterday's measurements (input voltage=50V, modulation index=98%, modulated frequency=200Hz):

     

    You see the three Gate Signals of the Top-IGBTs (blue, purple, green) and the ADC's MXO output (yellow) which is connected directly to the AINP input. So the faults are also on the multiplexed signal. As you can see in the picture, the frequency of the disturbance is 200Hz which is the modulated sinus frequency of the PWMs.

    I also measured the voltages on the channel inputs and they were free of interference. Also the ADC's supply voltages and the reference voltage are clean. Furthermore, there is no offset betwenn the DGND and the AGND. I don't know where the interference could come from else and am quite clueless at the moment.

    I'll tell you the ADC's operating data later this day and will also post an extract of the schematic.

  • Hello,

    the channel is changed with a frequency of 3.75kHz,  every channel is renewed in a rate of 750Hz. It is used in non automatic mode (channel is chosen manually).

  • Hi Tobias,

    Are you able to capture the schematic around the ADS7951 for us? 

    By the waveform on the output above, it seems that you are switching between four channels.  I see the ~3.75k/CH and the rep rate of ~750Hz for the most part.  There are several spots though where you seem to dwell on one channel longer, for instance on the left side where CH1 is high for about 80ns or so.  Is this part of your algorithm?  Can you possibly capture the SCLK, CS and SDI along with the MXO?

  • Hello,

    sorry for answering only now. I measured spikes on the chip select line. The distortions on the mux signal appear at spikes hitting the CS signal straight before a rising edge.

    What is inexplicable for me among other things is the amplitude of the distortions on the mux signal. I injected the reference voltage of 2.5V on all chanels of the ADC and nevertheless the distortion's amplitude reaches up to 6V. There is no signal over 5V on the ADC. Anyone an idea?

  • Hi Tobias,

    The overshoots you see may or may not be real - depends on how you have the board probed.  If you have good (and short) ground leads with low capacitance probes, you may be seeing overshoot simply due to the switching speeds of the clock, the /CS, the PWM - a host of actors can play into this.  Parasitic inductance and capacitance on the board can cause these sorts of problems.  If this amount of noise on the /CS input is real, the ADS7891 could be responding to perceived channel changes.  A series R on the CS input of say 100 ohms may help.  A small cap (a few pF?) to ground might be in order as well.