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AFE5801: When ADC sample rate is greater than SPI clock speed.

Ching Chuan Hsieh
Prodigy 50 points
Part Number: AFE5801
Other Parts Discussed in Thread: AFE5828

Hello,

I got one question when I was reading AFE5801 datasheet:

I noticed the maximum speed of SPI clock is 20MHz, and each ADC can reach 65MSPS sample rate. In case I would like to change setting of AFE5801 by SPI command when ADC is in converting work, it must has data-loss when SPI command is sending to the AFE chip. (Because ADC sample rate is greater than SPI clock speed)

Why the sampling rate is higher than data transmitting speed. is there any buffer in between? If yes, how is the buffer size?

Sincerely,

Ching-Chuan.

  • 0
    TI__Genius 12025 points

    Hi,

    Thank you for using AFE5801 device.

    As you can see from AFE5801 datasheet

    SPI's data and clock are not related to ADC's data and clock.

    ADC's data signal and clock signal are very precise 

    when you start to sample the ADC signal, then you can predict when you can receive the correct output data after some periods of clocks.

    However, although SPI has max 20MHz speed but does not require its data and clock the input signal and output signal's accuracy. From AFE5801 device, you can see besides ADC's data and clock signals, the following pins can be used for real timing signal. 

    RESET
    PDN 
    SYNC

    Thank you!

    Best regards,

    Chen

  • 0 in reply to Chen Kung
    Prodigy 50 points

    Dear Chen,

    Thanks for your reply, but maybe I didn’t describe my question well.

    What I concern is whether there is conflict between SPI input speed and LVDS output speed. If I input 65MHz to AFE5801 clock pin, would LVDS output for each bit (or each data set, e.g. “0~4095”) in 65MHz speed? If that so, assuming I want to adjust AFE5801 setting by SPI command (SPI clock in 20MHz) when LVDS continuously output, I might get some LVDS data that I don’t want before SPI command is fully transmitted to the AFE5801 chip, right?

     

    Sincerely,

    Ching-Chuan

  • 0 in reply to Ching Chuan Hsieh
    TI__Genius 12025 points

    Hi Ching-Chuan,

    How are you?

    Yes, you are right. The AFE5801 datasheet does not mention the timing between SPI starting time (nSEN)

    vs. ADC Clock starting time.

    You may try to run SPI as fast as you can (such as 20MHz SCLK)

    but during starting to enable your SPI also running your ADC clock, then

    how long or how many ADC clocks you need to wait a least until your data conversion is ready to run.

    Therefore, you can take a look at other device such as AFE5828 Datasheet page 83 Figure 90

    to explain you need to wait (at least) t8=100us (this is the example from AFE5828 device).

    Of course, please refer to AFE5801 datasheet page 8's "ADC latency Default, after reset" needs about 11 input clock cycles.

    so you need at least to wait t8 and/or 11 clock cycles before you can capture the valid data.

    To make sure the data you start to captured are valid or not

    is very important.

    Thank you!

    Best regards,

    Chen

  • 0 in reply to Chen Kung
    Prodigy 50 points

    Dear Chen,

    Thanks for your reply,

    but when I want to study AFE5828 datasheet from TI official website, I only can refer 7 pages. Could you send me the complete version to my email(d0911631912@kimo.com)?

    Thanks.

    Sincerely,

    Ching-Chuan.

  • 0 in reply to Chen Kung
    Prodigy 50 points

    Dear Chen,

    I already receive the data in my mailbox, thank you.

    Based on the previous question I ask, I listed some following questions below:

    Q1. As you said, "Yes, you are right.", but I still feel confused about LVDS output status, so I make more assumption for you. If I set AFE5801 output data format in 2's complement, input 65MHz clock, how many time period for sending one set output data, i.e. how many time period for completing sending one 12-bit value?

    Q2. When LVDS keep sending, I want to sending SPI commands to AFE5801. Due to SPI clock(20MHz) is slower than LVDS output clock rate(65MHz), it must have some LVDS output data I don't want before SPI commands are completely transmitted. Is there any buffer inside AFE5801 can store SPI command? Then I can transmit data to AFE5801 core from buffer instead of FPGA, it can shorten SPI commands transmitting time.

    Thanks for your patience, if you would like discuss with on the phone, I've already sent my phone number to your mailbox.

    Sincerely,

    Ching-Chuan.

  • 0 in reply to Ching Chuan Hsieh
    TI__Genius 12025 points

    Hi,

    Thanks for using AFE5801 device.

    for your question Q1:

    please look at the datasheet on page 9 (and page 8),

    when you starts to receive the sample N at that moment,

    inside AFE5801 device needs to wait 11 clock cycles

    and then you can capture its output digital data (from AFE5801 output pins)

    to capture your sample N data. But you also knows the capture output data

    rate will be 65MHz/2 * 12 (data rate).

    for your question Q2:

    Inside AFE5801 there is no either buffer or memory to store those SPI data inside.

    Once you turn off the power supply, you will need to re-setup AFE5801's register again.

    But after you setup the register (using SPI), it will keep the register values.

    Thank you!

    Have a nice day!

    Best regards,

    Chen