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ADS1274 / ADS1278 MCLK/SCK ratio

Filippo Bianchi
Prodigy 30 points

I have read in datasheet that "for best performance limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc...". My problem is that i need to use a differ ratio:

MCLK was received from an external clock generator, and SCK was generated by a microcontroller that use own clock.

For example, MCLK is 27MHZ and SCK 12.324 MHz (the two clock are completely different).

In what limitation can I occur?

 

Thanks,

Filippo Bianchi

  • 0
    TI__Mastermind 43915 points

    Hi Filippo,

    We recommend keeping the two clocks within a ratio of one another to keep the noise at a minimum. Having the clocks out of phase or out of ratio of one another will increase the noise but still keep the noise within spec (less than 12uV rms in HR mode). Otherwise, you should not have any other problems.

    Regards,

    Tony Calabria