ADS1158: Power up timing

Viktorija Cecil

Part Number: ADS1158
Other Parts Discussed in Thread: ADS1258

Team,

I’m trying to get some clarity on the power up timing for the ADS1158.

The datasheet sort of shows that a reset, whether with AVDD-AVSS or RESET command or pin, requires oscillator wake time + PLL lock time + 2^18 fclk cycles and taking PWDN pin high requires just the oscillator wake time + PLL lock time. This would give:

2^18*(1/15.729 MHz) = 16.6 ms for just the reset function but would still require the oscillator wake time and PLL lock time before the device is ready for any communication from the MCU. Is that correct?

How would one determine the PLL lock time?

Thanks

Viktorija

over 5 years ago

0 Bryan Lizon86 over 5 years ago

TI__Guru 53156 points

Hi Viktorija,

Let me look into this and get back to you

-Bryan

0 Bryan Lizon86 over 5 years ago in reply to Bryan Lizon86

TI__Guru 53156 points

Hi Viktorija,

Table 9 in the ADS1258 datasheet describes the wake up times under difference circumstances. You mentioned RESET in your original post, though these conditions relate to the PWDN pin or command as described in the image below.

PLL lock time is a small portion of the overall wakeup time, no more than 10-15% of the total time for a rough estimate. You can measure the entire oscillator/PLL wake up time by monitoring the time duration from power-down de-assert to master clock coming out to the pin. Since TOSC is given in the datasheet, the PLL lock time can then be determined.

-Bryan