CCS/AFE7225: Please delete! Thanks

Underwood, 

Please send me the configuration details. Are you using TI's version of the AFE7225EVM or are you using a custom board. If it's custom, we will need to take this offline so that you can share your schematic with me.

Can you please provide following details.

What is the desired TX and RX data rate? 

Frequency of CLK signal?

Please probe Vcm (pin 63). What is common mode voltage?

Regarding the FIFO try setting the x104register to x30 and see if anything changes.

Please report back your findings and additional details i requested to that i can better help to resolve this. 

Thanks

Yusuf 

Nope

Underwood, 

To answer your questions. 

Regarding the sync signal, you should toggle it from high to low. 

On your clock diagram, is the signal you labeled as "data" the  data clock present at DAC_DCLKP/N input pins? That data clock should be half that of the dac sampling clock but it it looks like its duty cycle changes in the scope shot you sent me. Can you ensure that the data clock is stable and referenced to the sampling clock so that the phase relationship between both clocks remains fixed. 

Yusuf