Other Parts Discussed in Thread: ADS8688,
Hi,
I am planning to use multiple ADS8688(A) chips in daisy chain for simultaneous sampling.
The *CS signal seems to control the start of conversion. Is the analog signal value saved to the sample/hold capacitor during the falling edge of *CS?
If that happens, then i guess the variability of the internal oscillator of each chip should not play any role and the multiple ADC arrays will be sampling trully simultaneously. Is that correct?
Thanks in advance!