DAC38RF80EVM: Does not sync when using provided KCU105 example design

Jacob,

From the DAC38RFxx clocking tab view, it appears you did not run the PLL Auto Tune since the PLL LF Voltage value shown is at "7". After configuring the DAC, click on the "PLL AUTO TUNE" button in the quick start tab of the GUI. If the PLL tunes properly, the PLL LF Voltage should show a value between 3-5. You cannot continue testing until the PLL LF Voltage is within this range.

The schematic has an error. C2 and C3 are installed and when using the DAC in PLL mode, the clock input is differential.

Regards,

Jim

Jim,

Thank you for that information; it definitely helped and I'm glad I don't need to manually set the single ended clock anymore. If I click the "PLL AUTO TUNE" button after the "CONFIGURE DAC" button and before the "Reset DAC JESD Core & SYSREF TRIGGER" button, the PLL LF Voltage is 5 instead of 7. The clocking tab is shown below. This also means the sync line from the DAC goes high as well, which is good news. I suspect the last thing that needs to be addressed is the ready signal not going high as shown in the new chip scope I produced. Please let me know what parameters you want me to look into, if any, or what signals I should hook up to my ILA to verify what is working.

Jacob,

Under the DAC38RF8x tab click on "Alarm Monitoring". Once this window opens, click on "Clear all errors and read". Let me know what this reports. What is this ready signal you are referring to? Do the serdes lanes show data coming out on all lanes? What is the DAC output look like? I would mask off all alarms so that the DAC does not force the output to mid-scale if an error occurs for now. Is TXENABLE high?

Regards,

Jim    

Jim,

After clicking "Clear all errors and read" I didn't seem to get anything in the report.

Regarding the ready signal, the chip scope provided in the KCU105 example design has 8 signals on it. Four of them are sine waves generated using DDS cores, 1 of them is a concatenation of those 4 signals, 1 of them is the 256 bits that get transferred to the DAC every clock cycle, 1 of them is the SYNC signal coming from the DAC, and the last one is a ready signal. If I look in the user guide for this example design, the chip scope section has pictures that have the sync line and the ready line being high. With your help, I was able to get the SYNC line to go high, but the ready line is still low. Below is a picture that shows all of the data signals being generated, the sync line being high, but the ready line being low.

I am unsure how to check to see if data is coming out on all of the serdes lanes. The output of both DAC is a DC signal at 0 volts. For masking the alarms, I checked all of the boxes in the DAC A and DAC B Alarm Masking windows. The result was the same, no output on the DAC and the ready signal was still low. That being said the "Alarm Mid-levels DAC" box is unchecked by default.

In the Digital (DAC A) and Digital (DAC B) tabs the "TX Enable" box is unchecked by default. I checked this box for both tabs but the result was the same, no output on the DAC and the ready signal was still low.

I hope that clarified things,

Jake

Jim,

Thanks for the help. I didn't realize Xilinx made the build; I thought it was a TI creation. I was trying to keep off of the Xilinx forums as long as I could, just based on their responsiveness to me in the past.

For anyone that wants to view the Xilinx thread I started on this issue, here is the link:

https://forums.xilinx.com/t5/Xilinx-IP-Catalog/JESD204-tx-tready-doesn-t-go-high/m-p/1104089

Jake

Jake,

I was incorrect regarding the KCU105 reference firmware. This was created by a third party vendor we use. When talking with them, they informed me the following:

"Please note that the design shared is for a particular JMODE and lane rate- 84111 & 7.68Gbps with FPGA reference clock of 192M and is not expected to work in any other mode or lane rate.

Can you confirm if the customer is targeting the same mode & lane rate?"

Are you attempting to use a different mode and or lane rate?

Regards,

Jim

Jim,

Thank you for continuing to look into this.

As you said, the JMODE, line rate, and reference clock on the FPGA from the build I got is 84111, 7.68Gbps, and 192MHz, respectively. From the Quick start menu for the DAC, you can see my JMODE is 84111, the SERDES line rate is 7680.00MHz (7.68GHz), and if you look on the clock outputs on the LMK page, I am dividing my input clock of 384MHz by two (192MHz) and that goes to my FPGAs reference clock. Pictures below:

Thank you,

Jake

Jake,

Please try the following steps on your setup:

1.       Make sure the steps are executed as per “KCU105 DAC38RF82 JESD Reference Design User Guide”.

The DAC38RF82 must be configured initially before doing a FW download as mentioned in chapter IV of the user's guide.

2.       Try to reset the Reference design FW by pressing the SW-5 reset button in KCU105 EVM once after FW download.

Then try a capture to see if tx_tready goes HIGH.

3.       Please let us know the status of the SYNC signal (stable or toggling) and tx_out_clk signal.

The status of these signals can be observed from the on-board LED’s ( D0 – SYNC and D4 – Tx_out_clk). Refer to attached word document.

4.       Attached is a firmware build with few signals probed in chip-scope .

Please let us know the status of the following probed signals for debug purposes.

a.       Tx_reset

b.      Common0/1_Qpll0_locked

c.       Tx_reset_gt

d.      Tx_reset_done

Please take a snap of the Hardware Manager window with these signals and sent it to us.

Regards,

Jim

LED Status.docxSupport_KCU105_DAC38RF84.zip

Jim,

Replying to your steps:

1. I am following the steps in the "KCU105 DAC38RF82 JESD REFERENCE DESIGN USER GUIDE" to the letter, with one small modification. I am programming the DAC before loading the firmware as chapter IV section 1 and 2 instructs me to do. However, after chapter IV section 3 but before I start section 4 I press the SW-5 button on the KCU105 EVM. I do this because I don't think the clocks generated from the JESD204 PHY IP core have started and resetting the firmware gives them a jump start. The reason I don't think the clocks have started is because the LEDs aren't on and the chipscope won't start. Both of these issues go away if I press the button, though.

2. As mentioned in the previous step, I do hit the button in my normal setup, but I still don't see the ready signal go high. I also press this button again after the chipscope is up (and the LEDs are on) and rerun the chipscope, but the result is the same.

3. Also mentioned in step 1 of this comment, the LEDs are off after programming the FPGA but turn on after pressing the SW-5 button (again because I think the clocks were off). Per the document you shared and chapter VI of the users guide, LED D0 is in fact on and stable, and LED D4 is on and blinking (toggling). So those two signals seem good to me.

4. With the new .bit and .ltx file you provided I took some chipscope captures. Same as in step 1, the LEDs were off and the chipscope wouldn't open after loading the firmware, but went back to expected operation after hitting SW-5. For the two scope captures I am providing, I pressed the "Run trigger immediate for this ILA core" button, as opposed to triggering on a specific signal changing. For example, I could have triggered off the change of the reset signals, but you didn't tell me to do that. If you would like me to do that, please let me know.

Thank you,

Jake