Hi,
We are planning to connect ADS1672 to Freescale iMX25 processor via standard SPI Interface. We want to sample at maximum rate which is 625 KSPS. I would like to know if the following design will work.
Provide CLK = 20 Mhz. Configure for Low-latency Date Rates with Fast-Response Configuration (last entry in Table 6 Page 17). If I set the START=1 (always convert), will DRDY signal toggle exactly at 625 KSPS? Can we reliably then use the DRDY to read data via SPI?
Thanks,
Harish