ADS1018-Q1: ADS1018-Q1:

Siddharth,

I'm sorry I missed this question last week.

1. The sampling capacitance value (CB) varies with the FSR. For an FSR value of ±2.048V, the sampling capacitance is about 0.8pF. This value includes both the actual sampling capacitor and parasitic capacitance in the device. This capacitance gets larger as the FSR gets smaller (for ±1.024V, ±0.512V, and ±0.256V) almost doubling with each change. This is why the input impedance, which comes from periodic capacitive sampling looks like the following:

2. The pin capacitance for all ADS1018 pins is modeled in the ADS1018 IBIS model. You can find the model (zipped up) here:

https://www.ti.com/lit/zip/sbam165

For information about the IBIS model structure, you can find information in this document:

http://www.ti.com/lit/an/snla046/snla046.pdf

In the model, the capacitance for each pin is shown as a combination of C_pkg and C_comp. The capacitance for the analog inputs are approximately 1.5 to 2pF each (without input sampling capacitance). There is some difference between the DGS and RUG packages, and the RUG capacitance will be a bit smaller. I would note that the PCB trace lines often have more capacitance than the device themselves.

Joseph Wu