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ADS130E08: ADS130E08

ARVINDA KUMAR
Prodigy 190 points
Part Number: ADS130E08

Hi,

I am using ADS130E08 as ADC in my project. if we read the datasheet its written that if VINP-VINN is greater than or equal to Vref then the digital output will be 7FFF.

in my application VINP(max):2.85V, VINN:1.65V, VIN(min):0.45V, Vref internal:2.4V, gain:2 with single ended mode

if I input 2.85V to the VINP, digital output is getting saturated at 72FA.

not getting full scale output during VINP:2.85V, is there any reason??

Thanks and regards

ARVINDA KUMAR

  • 0
    TI__Guru* 97585 points

    Arvinda,


    First, I would make the same measurement with PGA=1 to make sure that you can see the full scale range.

    I think what is happening is your signal is violating the input common-mode range of the PGA. This is described in the datasheet in section 9.3.4 on pages 22 and 23. The PGA is set up similar to the front end of an instrumentation amplifier. There are two amplifiers that impart gain from setting voltage across resistors just like in this figure:

    Because of this, the input common-mode voltage and the output common-mode voltage must be same. Normally, we say that the input common-mode voltage must be within the following range:

    This is taken from Equation 4 of the datasheet. This limitation is because the PGA can only amplify as large as the supplies. For your input signals, we can look at this graphically, showing the amplification against the supplies (presumably 0V to 3.3V).

    With AINP at 2.85V and AINN at 1.65V, the input common-mode voltage is at 2.25V. This input signal is 1.2V. The output of the PGA would be a 2.4V signal with the same common-mode voltage of 2.25V. This means that the negative output would be driven to 1.05V and the positive output would be driven to 3.45V.

    However, because the supply is only 3.3V, the positive output can't be driven that high. It will be limited to 3.3V (or really 100mV within 3.3V). If we say that the output goes to 3.2V, we can calculate that the PGA will amplify the signal to only 3.2V-1.05V=2.15V. This will give an ADC measurement of:

    Output Code = (2.15V/2.4V)*2^15 = 72AAh

    Regardless, I think the PGA gain is limited by the supply because of the common-mode input range.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 190 points

    Joseph 

    thank you for your response

    since  i am using in the single ended mode, common mode voltage will be same as the AINN?

    AINN is fixed at 1.65V and AINP is swings from 0.45V to 2.85V, and PGA=2

    so the peak to peak voltage will be 0.45V to 2.85V right?

  • 0 in reply to ARVINDA KUMAR
    TI__Guru* 97585 points

    Arvinda,


    The common-mode input voltage is always the midpoint between the positive input and the negative input. It's an instantaneous value of the input, not an average value. In my previous diagram, it shows how the input values at that instant would cause the amplifier to drive the output into the supply rail.

    If AINN is set at 1.65V and AINP swings from 0.45V to 2.85V, then the input common-mode voltage will also vary. You can calculate it below

    Low input common-mode voltage = (1.65V+0.45V)/2 = 1.05V
    High input common-mode voltage = (1.65V+2.85V)/2 = 2.25V

    So with the AINP swinging from 0.45V to 2.85V, the common-mode input voltage varies from 1.05V to 2.25V.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 190 points

    Joseph

    Thank you for you response

    was not knowing that input common voltage will also very.

    thank you