I'm wondering what the current draw on the IOVdd line is. The datasheet lists it as 10uA during 'normal mode' but does the current draw change when sending DAC updates over the IO lines? If I were sending a constant stream of SPI data at 50 MHz, would the IOVdd current draw still be 10uA, and if not what would it be? I'm wondering if I can use a resistor voltage divider off the the AVDD line to generate IOVdd, or if I need a real voltage regulator to generate that voltage. Also, on page 15 of the datasheet, it says "For lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND voltages". Would this also affect the draw on IOVdd and if so, how is that calculated?
Thank you,