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DAC8554: Current draw on IOVdd @1MSPS

Part Number: DAC8554

I'm wondering what the current draw on the IOVdd line is. The datasheet lists it as 10uA during 'normal mode' but does the current draw change when sending DAC updates over the IO lines? If I were sending a constant stream of SPI data at 50 MHz, would the IOVdd current draw still be 10uA, and if not what would it be? I'm wondering if I can use a resistor voltage divider off the the AVDD line to generate IOVdd, or if I need a real voltage regulator to generate that voltage. Also, on page 15 of the datasheet, it says "For lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND voltages". Would this also affect the draw on IOVdd and if so, how is that calculated?

Thank you,

  • Hi Bren,

    Datasheet specifies IOVDD current for mid code and logic levels close to IOVDD.

    Generally speaking, if your logic levels less than IOVDD, you can expect a higher current draw form IOVDD supply. Lets say IOVDD is 5V and you are interfacing this device from microcontroller which is operating with 3.3V supply, in this case definitely you are going to see higher IOVDD current.

    Also, when bit switches from logic high to logic low or vice versa, you will see a transient current from IOVDD as well. Due to this we don't recommend deriving your IOVDD supply using resistor divider from AVDD.

    Whatever datasheet specifies in page 15 is applicable to any digital circuits, not only DAC.

    Regards,

    AK